Semiconductor device having planar transistor and FinFET

A device, comprising:

• a non-planar field effect transistor (FET) on a first region of a substrate, the non-planar FET comprising a first source region, a first drain region, and a first gate between the first source region and the first drain region;
• a planar-FET on a second region of the substrate, the planar-FET comprising a second source region, a second drain region, and a second gate between the second source region and the second drain region,
• wherein a bottommost position of the first source region is lower than a bottommost position of the second source region;
• a first dielectric region directly below the first gate of the non-planar FET;
• and
• a second dielectric region directly below the second gate of the planar-FET, wherein the second dielectric region is continuous with the first dielectric region, and the first source region is an epitaxial region having a width varying as a function of height, and the varying width of the epitaxial region has a maximum value at a position lower than a top surface of the second dielectric region.

A device, comprising:

• a first transistor on a substrate, and comprising first source/drain regions, a first channel region between the first source/drain regions, and a first gate on multiple sides of the first channel region;
• a second transistor on the substrate, and comprising second source/drain regions, a second channel region between the second source/drain regions, and a second gate on a top side of the second channel region;
• a first gate spacer spacing the first gate from one of the first source/drain regions;
• a second gate spacer spacing the second gate from one of the second source/drain regions, wherein the second gate spacer has a bottom surface higher than a bottom surface of the first gate spacer;
• and
• an isolation structure between the first transistor and the second transistor, the isolation structure having a stepped top surface having a higher region and a lower region lower than the higher region, the lower region being directly below the first gate, and the higher region being directly below the second gate, wherein a depth of the second source/drain regions of the second transistor is smaller than a height difference between the higher region and the lower region of the stepped top surface of the isolation structure.