Method and system of forming integrated circuit

A system for forming a three-dimensional (3D) integrated circuit (IC) comprising a first chip package and a second chip package stacked over the first chip package, the system comprising:

• a design tool including instructions to provide a first circuit layout corresponding to the first chip package and a second circuit layout corresponding to the second chip package, wherein the first circuit layout and the second circuit layout include a f first sub-power network and a second sub-power network, respectively, and the first sub-power network is coupled to the second sub-power network through a first path and a second path;
• a verification tool including instructions to obtain conductivity information of the first path and the second path, and perform a power simulation upon the first sub-power network, the second sub-power network, and at least one of the first path and the second path based on the conductivity information comprising simulating applying a current to only one of the first path and the second path or simulating applying a first sub-current to the first path and applying a second sub-current to the second path;
• and
• a fabricating device arranged to fabricate the 3D IC according to the first circuit layout and the second circuit layout.

A system for forming a three-dimensional (3D) integrated circuit (IC) including a first chip package and a second chip package stacked over the first chip package, the system comprising:

• a design tool including instructions to provide a first circuit layout corresponding to the first chip package and a second circuit layout corresponding to the second chip package, wherein the first circuit layout and the second circuit layout include a f first sub-power network and a second sub-power network, respectively;
• a verification tool including instructions to transform the first sub-power network and the second sub-power network into a first power network and perform a first power simulation upon the first power network including simulating applying a first current to a first load region, and transform the first sub-power network and the second sub-power network into a second power network different from the first power network and perform a second power simulation upon the second power network including simulating applying a second current to the second load region;
• and
• a fabricating device arranged to fabricate the IC according to the first circuit layout and the second circuit layout,
• wherein each of the first and second sub-power networks comprises a densely meshed region and a roughly meshed region.