Address latch, address control circuit and semiconductor apparatus including the address control circuit
AssigneeSK hynix Inc.
InventorJi Eun Kim
Life of this patent
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Abstract
Disclosed are an address latch, an address control circuit, and a semiconductor apparatus including the address control circuit. The address latch includes a first address processing unit and a second address processing unit. The first address processing unit latches an external address signals to output first latched signals through an output node based on a read command and a write command. The second address processing unit latches the external address signals based on the read command with a burst length set to a first value and outputs second latched signals through the output node based on an internal read command.
Claims17
An address latch comprising:
- a first address processing unit configured to latch external address signals to output first latched signals through an output node based on a read command and a write command;
- and
- a second address processing unit configured to latch the external address signals based on the read command with a burst length that is set to a first value and configured to output second latched signals through the output node based on an internal read command.
An address control circuit comprising:
- a read/write combined address latch configured to latch external address signals based on a read command or a write command to output first latched signals through a first output line and configured to latch the external address signals based on the read command with a burst length set to a first value to output second latched signals, according to an internal read command, through the first output line;
- a pipe register configured to store, therein, signals that are output through the first output line during a write operation of a semiconductor apparatus based on a plurality of input/output control signals and configured to output the stored signals through a second output line that is coupled to the first output line;
- and
- a decoder configured to decode signals, which are output through the second output line, to generate at least one of a bank group address, a bank address, and a column address.
A semiconductor apparatus comprising:
- a memory region including a plurality of memory cells, which are divided into a plurality of memory banks;
- a data input/output circuit coupled to the memory region and configured to exchange data with the memory region or an external device;
- an address control circuit configured to latch external address signals, which are input from the external device, according to a read command or a write command, to output first latched signals through a first output line, configured to latch the external address signals, according to the read command with a burst length set to a first value, to output second latched signals, according to an internal read command, through the first output line, and configured to decode signals, which are output through the first output line, to generate a bank group address, a bank address, and a column address;
- and
- an address decoder configured to decode the bank group address, the bank address, and the column address to access the memory region based on a result of the decoding.
Dependencies are inferred from the claim text.