Semiconductor memory device and memory system including the same

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control the semiconductor memory device,
• wherein the semiconductor memory device includes:
• a quadrature error correction circuit configured to perform a relocking operation to lock a second corrected clock signal to a first corrected clock signal based on a first command from the memory controller in a second operation mode, wherein the first corrected clock signal and the second corrected clock signal have a phase difference of 90 degrees with respect to each other and are generated based on first through fourth clock signals in a first operation mode.

A method of operating a semiconductor memory device including a quadrature error correction circuit, the method comprising:

• generating a first code by performing a locking operation, in the quadrature error correction circuit, in response to an initialization command;
• storing the first code in each of plurality of delay controllers in the quadrature error correction circuit;
• generating a relock signal based on detecting a duty error between a data clock single and a strobe signal which is generated based on a first corrected clock signal and a second corrected clock signal which are generated based on the first code;
• generating a second code by performing a relocking operation in response to the relock signal, in the quadrature error correction circuit;
• storing the second code in each of the plurality of delay controllers;
• and
• locking the second corrected clock signal to the first corrected clock signal based on the second code.