Far end driver for memory clock

A memory device, comprising:

• a plurality of memory cells in a plurality of rows in a memory array;
• a first memory clock driver disposed on a first side of the plurality of rows of the memory array, and
• a second memory clock driver disposed on a second side, opposite to the first side of the plurality of rows of the memory array, wherein the first and second memory clock drivers are configured to transmit a word line clock signal, in response to a master clock signal, to activate a row of memory cells in the plurality of rows of the memory array using the first and second memory clock drivers, and
• a row selection circuit configured to select a row of memory cells in the plurality of rows of the memory array using an address of the row of memory cells, wherein the row selection circuit includes:
• a first logical gate configured to receive the address;
• a second logical gate coupled to an output of the first logic gate and configured to receive the word line clock signal;
• and
• a third logical gate coupled between the output of the second logical gate and the row of memory cells.