Computing-in-memory circuitry

A computing-in-memory circuitry, comprising:

• a plurality of digital-to-analog converters, at least one of the digital-to-analog converters converting external data to input data, each of the digital-to-analog converters connecting in series with a corresponding plurality of output capacitor pairs;
• a plurality of computing arrays, at least one of the computing arrays receiving the input data from both ends and executing a computation to output a first computing value;
• a plurality of charge processing networks, at least one of the plurality of charge processing networks receiving and accumulating the first computing value over a predetermined time interval through a plurality of switching pairs in series with the output capacitor pairs, wherein the charge processing networks evenly distribute charges of the first computing value to at least one of the selected output capacitor pairs, and compare a voltage difference between two ends of the at least one of the output capacitor pairs to output a second computing value.