Integrated circuit chip and die test without cell array

An integrated circuit chip comprising:

• a first data node and a second data node;
• a first latch circuit and a second latch circuit configured to store data inputted through the first and second data nodes, respectively;
• and
• a transmission circuit configured to alternately transmit data stored in the first and second latch circuits to the first data node in response to a selection signal, during a test operation, the transmission circuit comprising:
• a selector having first and second data inputs, a selection signal input, and a data output, the selector configured to operatively connect one of the first and second data inputs to the data output responsive to its receipt of the selection signal;
• and
• a read driver configured to couple a data signal output from the selector to the first data node in response to a read data strobe signal;
• the integrated circuit chip additionally comprising:
• a selection signal generation circuit, which is configured to provide the selection signal responsive to a test operation signal, a repair signal and a read data strobe signal.

A memory device comprising:

• a first integrated circuit chip;
• and
• a plurality of second integrated circuit chips stacked over the first integrated circuit chip, wherein the first and second integrated circuit chips transmit/receive data through a plurality of through electrodes formed through the first integrated circuit chip and through the plurality of second integrated circuit chips,
• wherein the first integrated circuit chip comprises:
• a decoding circuit configured to generate a read data strobe signal by synchronizing a read command signal with a clock, during a read operation;
• a divider circuit configured to generate a divided signal by dividing the read data strobe signal;
• a transmission circuit comprising a selector having first and second data inputs, a selection signal input and a data output, the selector being configured to couple one of the first and second data inputs to the data output, in response to a selection signal received at the selection signal input;
• and
• a read driver configured to couple a data signal output from the selector to one of two data lines, which are coupled to the first data node, in response to the read data strobe signal;
• the memory device additionally comprising a selection signal generation circuit configured to provide the selection signal responsive to:
• a test operation signal, a repair signal and a read data strobe signal.

A method of performing a wafer level test on an integrated circuit chip having no cell array by utilizing a repair circuit configured to repair defective through electrodes to generate a test signal during the wafer level test, the method comprising:

• generating a toggling signal based on a read data strobe signal;
• providing two through electrodes coupled with two latch circuits configured to store test data from the coupled through electrodes;
• providing the toggling signal to a through electrode repair circuit as a selection signal, wherein the repair circuit is configured to select one of the two through electrodes in response to the logic level of the toggling signal;
• and
• during the wafer level test, generating the test signal by outputting the logic levels of the two latch circuits in response to the toggling signal.