Error compensation circuit for analog capacitor memory circuits

Abstract

An error compensation circuit for analog capacitor memory circuits includes a first transistor and a second transistor with gates connected respectively to top and bottom of an analog memory capacitor to read a voltage charged in the analog memory capacitor; a first switch and a second switch connected respectively to the first transistor and the second transistor to select the voltage to read; a first capacitor and a second capacitor to charge an electric charge to compensate or refresh the analog memory capacitor according to on/off of the first switch and the second switch; and an input terminal connected to sources of the first transistor and the second transistor to apply the voltage to operate the circuit. Accordingly, it is possible to compensate for an unintended phenomenon of the analog capacitor memory or refresh a change in memory value caused by leakage.

Dependencies are inferred from the claim text.