Improving reliability of verify operation for verifying program pulse operation of NAND flash memory device

A memory system, comprising:

• a memory device including a plurality of pages coupled to a plurality of word lines, respectively;
• and
• a memory controller configured to:
• control the memory device to repeatedly perform a program loop including a program pulse operation and a verify operation when a program command and an address are received, the program pulse operation comprising applying a program voltage to a selected word line corresponding to the address, among the plurality of word lines, and applying a program pass voltage to unselected word lines, the verify operation comprising applying a verify voltage to the selected word line and applying a verify pass voltage to the unselected word lines;
• and
• increase a level of the program voltage applied to the selected word line and a level of the verify pass voltage applied to the unselected word lines whenever the memory device performs the program loop until a pass signal is received indicating that the program pulse operation has passed according to the verify operation, wherein the unselected word lines include both word lines coupled to programed pages and word lines coupled to erased pages.

A method of operating a memory device including a memory block, the method comprising:

• receiving a program command and an address;
• performing a program pulse operation and a verify operation sequentially during a first program loop, the program pulse operation comprising applying a program voltage to a selected word line corresponding to the address, among a plurality of word lines coupled to a plurality of pages included in the memory block, respectively, the verify operation comprising applying a verify voltage corresponding to the program voltage to the selected word line and applying a verify pass voltage to unselected word lines;
• and
• performing the program pulse operation in which a level of the program voltage is increased and the verify operation in which a level of the verify pass voltage is increased sequentially during a second program loop when threshold voltages of memory cells included in a page coupled to the selected word line are greater than a reference level and less than a target level higher than the reference level, wherein the unselected word lines include both word lines coupled to programed pages and word lines coupled to erased pages.