NAND flash memory device and method of reducing program disturb thereof

A memory system, comprising:

• a memory device configured to store data and comprising:
• memory strings each comprising a drain select gate (DSG) transistor and memory cells;
• and
• a peripheral circuit coupled to the memory strings and configured to, in a program/verify cycle:
• program a target memory cell of the memory cells in a select memory string of the memory strings;
• after programming the target memory cell, verify the target memory cell using one or more verify voltages comprising an initial verify voltage;
• compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result;
• and
• control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the target memory cell,
• wherein to control the DSG transistor, the peripheral circuit is further configured to, in the program/verify cycle, in response to the comparing result indicative of the initial verify voltage being equal to or lower than the threshold verify voltage, turn on the DSG transistor in the unselect memory string in an interval between an end of programming and a start of verifying the target memory cell,
• wherein the initial verify voltage is a maximum voltage of the one or more verify voltages;
• and
• a memory controller coupled to the memory device and configured to control operations of the memory strings through the peripheral circuit.

A method for operating a memory device, the memory device comprising memory strings each comprising a drain select gate (DSG) transistor and memory cells, the method comprising, in a program/verify cycle:

• programming a target memory cell of the memory cells in a select memory string of the memory strings;
• after programming the target memory cell, verifying the target memory cell using one or more verify voltages comprising an initial verify voltage;
• comparing the initial verify voltage with a threshold verify voltage so as to obtain a comparing result;
• and
• controlling, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the target memory cell,
• wherein controlling the DSG transistor comprises, in the program/verify cycle, in response to the comparing result indicative of the initial verify voltage being equal to or lower than the threshold verify voltage, turning on the DSG transistor in the unselect memory string in an interval between an end of programming and a start of verifying the target memory cell, and
• wherein the initial verify voltage is a maximum voltage of the one or more verify voltages.