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US 12,009,025 B2Granted
Weak precharge before write dual-rail SRAM write optimization
AssigneeAdvanced Micro Devices, Inc.
InventorsTawfik Ahmed, Andrew J. Robison, Russell J. Schreiber
Life of this patent
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Abstract
A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.
Claims19
A method for accessing a memory cell, the method comprising:
- enabling precharging of a bit line of the memory cell before a next access of the memory cell;
- disabling the precharging after a first interval if the next access is a write;
- and
- disabling the precharging after a second interval if the next access is a read, the first interval being shorter than the second interval,
- wherein the bit line is precharged to a memory cell power supply voltage in response to the next access being a read or the next access being a write after a read access, and
- wherein the bit line is precharged to a level less than the memory cell power supply voltage prior to a write column select signal cutting off the precharging of the bit line and driving a complementary bit line to ground in response to the next access being a write after a write access.
3 more elements
A memory comprising:
- a memory cell coupled to a bit line and responsive to a bit line precharge control signal, a write column select signal, and a word line control signal;
- and
- a control circuit configured to generate the bit line precharge control signal, the write column select signal, and the word line control signal to precharge the bit line before a next access of the memory cell, disable the precharging after a first interval if the next access is a write, and disable the precharging after a second interval if the next access is a read, the first interval being shorter than the second interval,
- wherein the bit line is precharged to a memory cell power supply voltage in response to the next access being a read or the next access being a write after a read access, and
- wherein the bit line is precharged to a level less than the memory cell power supply voltage prior to the write column select signal cutting off the precharging of the bit line and driving a complementary bit line to ground in response to the next access being a write after a write access.
2 more elements
Dependencies are inferred from the claim text.