Circuit for reading out data, method for reading out data and memory
AssigneeChangxin Memory Technologies, Inc.
InventorsXianjun Wu, Weibing Shang
Life of this patent
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AssigneeChangxin Memory Technologies, Inc.
InventorsXianjun Wu, Weibing Shang
Estimating the term…
A circuit includes a delay generation circuit. The delay generation circuit is configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and data transmission delay of each of the storage areas, and generate a grab enable signal based on all the sub-grab signals. A time interval between a time when the read-write control circuit receives data transmitted from each of the storage areas by a global data line and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range. The read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal. Therefore, the tCCD of the DRAM is optimized.
A circuit for reading out data, applicable for a memory, wherein the memory comprises a read-write control circuit, a column decoding circuit and a plurality of storage areas, and the circuit comprises:
A method for reading out data, applicable for a data readout circuit, comprising:
A memory, comprising:
Dependencies are inferred from the claim text.