Device and method for performing matrix operation

A system for implementing a matrix operation, the system comprising:

• a memory array having a plurality of memory cells arranged logically in rows and columns, each of the plurality of memory cells having an input end, an output end, and a control end;
• a plurality of input lines, each connected to the input ends of a respective row of the memory cells;
• a plurality of output lines, each connected to the output ends of a respective column of the memory cells;
• a plurality of select lines, each connected to the control ends of a respective row of the memory cells;
• and
• an input interface connected to the plurality of input lines and adapted to sequentially apply a plurality of sets of input signals, each set indicative of a respective column or row of values of elements of a matrix, to the input lines;
• an output interface connected to the plurality of output lines and adapted to receive from the output lines the elements stored in respective columns of the memory cells;
• and
• a selection signal interface connected to the plurality of select lines and adapted to supply selection signals to the select lines,
• wherein the output interface or selection signal interface, or both cooperatively, are adapted to select a column of the plurality of memory cells to enable the column of the plurality of memory cells to store a set of data corresponding to each respective one of the sets of input signals applied to the input lines,
• wherein the selection signal interface is adapted to supply a voltage of a first level to all of the selection lines, and the output interface is adapted to supply a voltage of a second level to one of the output lines and a voltage of the first level to the remaining output lines,
• wherein the memory elements in the memory array are adapted to be able to store the elements supplied by the input interface through the respective input lines when a voltage of the first level is applied to the control end and a voltage of the second level is applied to the output end, and
• wherein the memory elements in the memory array are adapted to be unable to store the elements supplied by the input interface through the respective input lines when a voltage of the first level is applied to both the control end and the output end.

A system for processing an input data array having one or more one-dimensional data arrays, each having a set of multi-bit elements, the system comprising:

• a plurality of single-bit array processing systems, each comprising:
• a memory array having a plurality of memory cells arranged logically in rows and columns, each of the plurality of memory cells having an input end, an output end, and a control end;
• a plurality of input lines, each connected to the input ends of a respective row of the memory cells;
• a plurality of output lines, each connected to the output ends of a respective column of the memory cells;
• and
• a plurality of select lines, each connected to the control ends of a respective row of the memory cells;
• an input interface connected to the plurality of input lines of the plurality of single-bit array processing systems and adapted to sequentially apply a plurality of sets of input signals, each set indicative of a respective column or row of values of elements of a matrix, to supply a bit of each of the multi-bit elements of one of the one-dimensional data arrays to each of the respective input lines;
• an output interface connected to the plurality of output lines of each single-bit array processing system and adapted to receive from the output lines the elements stored in respective columns of the memory cells;
• and
• a selection signal interface connected to the plurality of select lines of each single-bit processing system and adapted to supply selection signals to the select lines;
• wherein the output interface and selection signal interface are adapted to select a column of the plurality of memory cells in each of the plurality of single-bit array processing systems to enable the column of the plurality of memory cells to store a set of data corresponding to each respective one of the sets of input signals applied to the input lines;
• and
• wherein the input interface and selection signal interface are adapted to select rows of the plurality of memory cells in each of the plurality of single-bit array processing systems to enable, row-by-row, the plurality of memory cells to output the elements stored in of the plurality of memory cells to the output interface.

A method of implementing an array operation, the method comprising:

• sequentially applying a plurality of sets of input signals, each set indicative of a respective subset of values of elements of an array, to wordlines of a memory array having a plurality columns and rows of memory cells, each row of the memory cells being associated with a respective one of the wordlines;
• storing in the memory array, column-by-column of the memory array, a set of data corresponding to a respective one of the sets of input signals applied to the wordlines;
• and
• reading from the memory array, row-by-row of the memory array, the elements written to the memory cells.