Memory device generating optimal write voltage based on size of memory cell and initial write voltage

A method of operating a memory device, the method comprising:

• programming memory cells of the memory device to a first state, and iteratively counting fail bits for the memory cells programmed to the first state using a plurality of reference resistances to generate a first counting result;
• programming the memory cells of the memory device to a second state, and iteratively counting fail bits for the memory cells programmed to the second state using the plurality of reference resistances to generate a second counting result;
• selecting one of the plurality of reference resistances as an optimal reference resistance in response to the first counting result and the second counting result;
• and
• determining a write voltage for the memory device in relation to the optimal reference resistance and an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.

A memory device comprising:

• a memory cell array including a first memory cell region and a second memory cell region;
• a column decoder configured to select a bit line connected to a selected memory cell among memory cells in the first memory cell region;
• a row decoder configured to drive the bit line connected to the selected memory cell;
• a voltage generator configured to generate a code corresponding to a program voltage for the memory device;
• and
• a write driver configured to drive a program current storing data in the selected memory cell in response to the code, and provide the program current to the selected memory cell through the bit line,
• wherein the second memory cell region stores a value defining the program voltage and another value defining an optimal reference resistance,
• the optimal reference resistance is determined in relation to a first counting result of fail bits for memory cells in the first memory cell region programmed to a first state using a plurality of reference resistances, and a second counting result of fail bits for memory cells in the first memory cell region programmed to a second state using the plurality of reference resistances, and
• the program voltage is determined in relation to the optimal reference resistance and an initial program voltage applied to at least one of memory cells of the first memory cell region and memory cells of the second memory cell region.