US 12,008,975 B2Granted

Display device and operating method thereof

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsSusumu Kawashima, Kouhei Toyotaka, Kei Takahashi

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Abstract

A display device that achieves both high-accuracy sensing by a touch sensor unit and smooth input using the touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs touch sensing operation at a different timing from display image rewriting by the display unit, whereby the high-accuracy sensing can be achieved. The display unit has a function of rewriting a display image only in a region that needs to be rewritten. In the case where the entire display region is not necessarily rewritten, the time for the sensing operation by the touch sensor unit can be lengthened, whereby the smooth input can be achieved.

Claims6

Dependent claims

A display device comprising:

a display unit, the display unit comprising:
a touch sensor;
a pixel array;
a source driver electrically connected to a first demultiplexer;
and
a plurality of gate drivers sandwiching the pixel array, one of the plurality of gate drivers comprising a first shift register,
wherein the first shift register comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
and
a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring,
wherein the first demultiplexer comprises a ninth transistor comprising silicon in a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, the first wiring, and one electrode of a first capacitor,
wherein a gate of the first transistor is electrically connected to the other electrode of the first capacitor and one of a source and a drain of the third transistor,
wherein a gate of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring, one of a source and a drain of the eighth transistor, one of a source and a drain of the sixth transistor, and one electrode of a second capacitor,
wherein a gate of the fourth transistor is electrically connected to the fifth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor, a gate of the fifth transistor, and a gate of the sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor, and
wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor.

18 more elements

A display device comprising:

a display unit, the display unit comprising:
a touch sensor;
a pixel array comprising a plurality of pixels, one of the plurality of pixels comprising a light-emitting element;
a source driver electrically connected to a first demultiplexer;
and
a plurality of gate drivers sandwiching the pixel array, one of the plurality of gate drivers comprising a first shift register,
wherein the first shift register comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
and
a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring,
wherein the plurality of gate drivers and the pixel array are provided over a flexible substrate,
wherein the first demultiplexer comprises a ninth transistor comprising silicon in a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein a first clock signal is supplied to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,
wherein a first output signal is output from the first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, the first wiring, and one electrode of a first capacitor,
wherein a gate of the first transistor is electrically connected to the other electrode of the first capacitor and one of a source and a drain of the third transistor,
wherein a gate of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring, one of a source and a drain of the eighth transistor, one of a source and a drain of the sixth transistor, and one electrode of a second capacitor,
wherein a gate of the fourth transistor is electrically connected to the fifth wiring,
wherein a second clock signal is supplied to the fifth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor, a gate of the fifth transistor, and a gate of the sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor, and
wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor.

22 more elements

A display device comprising:

a display unit, the display unit comprising:
a touch sensor;
a pixel array comprising a plurality of pixels, one of the plurality of pixels comprising a light-emitting element;
a source driver comprising a first shift register, an output terminal of the source driver being electrically connected to a first demultiplexer;
and
a plurality of gate drivers sandwiching the pixel array, one of the plurality of gate drivers comprising a second demultiplexer and a second shift register,
wherein the second shift register comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
and
a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring,
wherein the plurality of gate drivers and the pixel array are provided over a flexible substrate,
wherein the second demultiplexer comprises a ninth transistor comprising silicon in a channel formation region,
wherein the one of the plurality of pixels comprises a tenth transistor comprising an oxide semiconductor in a channel formation region and an eleventh transistor comprising silicon in a channel formation region,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein a first clock signal is supplied to the second wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,
wherein a first output signal is output from the first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, the first wiring, and one electrode of a first capacitor,
wherein a gate of the first transistor is electrically connected to the other electrode of the first capacitor and one of a source and a drain of the third transistor,
wherein a gate of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring, one of a source and a drain of the eighth transistor, one of a source and a drain of the sixth transistor, and one electrode of a second capacitor,
wherein a gate of the fourth transistor is electrically connected to the fifth wiring,
wherein a second clock signal is supplied to the fifth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor, a gate of the fifth transistor, and a gate of the sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor,
wherein a sixth wiring is electrically connected to one of a source and a drain of the eleventh transistor,
wherein the first wiring is electrically connected to a gate of the eleventh transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to one electrode of a third capacitor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to one electrode of the light-emitting element, and
wherein a first gate of the tenth transistor is electrically connected to a second gate of the tenth transistor.

28 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/142,370Filed 2 May 2023 · continuation
Priority: JP 2016-22932625 Nov 2016
Published: US 2023/0298537 A121 Sep 2023
Granted: 11 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

G09G 3/3677
Details of drivers for scan electrodes: suitable for active matrices only
G06F 3/0418
Control or interface arrangements specially adapted for digitisers: for error correction or compensation, e.g. based on parallax, calibration or…
G06F 3/04184
For error correction or compensation, e.g. based on parallax, calibration or alignment: synchronisation with the driving of the display or the…
G06F 3/0443
By capacitive means: using a single layer of sensing electrodes

Family

Application15/819,347Parent of this continuation · filed 21 Nov 2017
Application17/177,445Parent of this continuation · filed 17 Feb 2021
US 11,062,667 B2Parent of this continuation · filed 13 Jul 2021
Application17/836,244Parent of this continuation · filed 9 Jun 2022
US 11,361,726 B2Parent of this continuation · filed 14 Jun 2022
US 2023/0298537 A1Pre-grant publication · published 21 Sep 2023
US 11,715,438 B2Parent of this continuation
US 10,930,237 B2Related patent
US 11,676,555 B2Related patent
US 2018/0151144 A1Published application
US 2021/0193071 A1Published application
US 2022/0319462 A1Published application
US 12,008,975 B2This patent

From the US filing history. Foreign family members aren’t listed.

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