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US 12,008,957 B2Granted
Pixel compensation circuit, display panel and display device
AssigneeShenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
InventorLiuqi Zhang
Life of this patent
Estimating the term…
Abstract
A pixel compensation circuit, a display panel and a display device are disclosed according to an embodiment of the present disclosure. Through detecting the threshold voltage of the driving transistor and offsetting the threshold voltage of the driving transistor from the driving current of the light emitting unit, the driving current becomes unrelated to the threshold voltage of the driving transistor. This could solve the conventional issues of uneven display effect when the driving current of the light emitting unit is affected by the shift of the threshold voltage of the driving transistor.
Claims18
A pixel compensation circuit, comprising:
- a driving transistor, a data write-in transistor, a reset transistor, a compensation transistor, and a storage capacitor;
- wherein a gate of the driving transistor is connected to a first node and a source of the driving transistor is connected to a negative electrode of a power source;
- wherein a gate of the data write-in transistor is connected to a write-in signal input end, a source of the data write-in transistor is connected to a data signal input end, and a drain of the data write-in transistor is connected to a second node;
- wherein a gate of the reset transistor is connected to a reset signal input end, a source of the reset transistor is connected to a reference signal input end, and a drain of the reset transistor is connected to the second node;
- wherein a gate of the compensation transistor is connected to a reset signal input end, a source of the compensation transistor is connected to a positive electrode of the power source, and a drain of the compensation transistor is connected to the first node;
- and
- wherein a first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the second node;
- wherein during a first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned on;
- wherein during a second period after the first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned off;
- wherein during a third period after the second period, the reset transistor, the compensation transistor, the data write-in transistor and the driving transistor are all turned off;
- wherein during a fourth period after the third period, the driving transistor and the data write-in transistor are turned on, and the compensation transistor and the reset transistor are turned off;
- wherein during a fifth period after the fourth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off;
- and
- wherein during a sixth period after the fifth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off.
11 more elements
A display panel, comprising:
- a light emitting unit, having an anode connected to a positive electrode of a power source and a cathode;
- and
- a pixel compensation circuit, connected to the cathode of the light emitting unit and, comprising a driving transistor, a data write-in transistor, a reset transistor, a compensation transistor, and a storage capacitor;
- wherein a gate of the driving transistor is connected to a first node and a source of the driving transistor is connected to a negative electrode of a power source, a drain of the driving transistor is connected to the cathode of the light emitting unit;
- wherein a gate of the data write-in transistor is connected to a write-in signal input end, a source of the data write-in transistor is connected to a data signal input end, and a drain of the data write-in transistor is connected to a second node;
- wherein a gate of the reset transistor is connected to a reset signal input end, a source of the reset transistor is connected to a reference signal input end, and a drain of the reset transistor is connected to the second node;
- wherein a gate of the compensation transistor is connected to a reset signal input end, a source of the compensation transistor is connected to a positive electrode of the power source, and a drain of the compensation transistor is connected to the first node;
- and
- wherein a first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the second node;
- wherein during a first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned on;
- wherein during a second period after the first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned off;
- wherein during a third period after the second period, the reset transistor, the compensation transistor, the data write-in transistor and the driving transistor are all turned off;
- wherein during a fourth period after the third period, the driving transistor and the data write-in transistor are turned on, and the compensation transistor and the reset transistor are turned off;
- wherein during a fifth period after the fourth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off;
- and
- wherein during a sixth period after the fifth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off.
13 more elements
A display device, comprising a display panel, the display panel comprising:
- a light emitting unit, having an anode connected to a positive electrode of a power source and a cathode;
- and
- a pixel compensation circuit, connected to the cathode of the light emitting unit and, comprising a driving transistor, a data write-in transistor, a reset transistor, a compensation transistor, and a storage capacitor;
- wherein a gate of the driving transistor is connected to a first node and a source of the driving transistor is connected to a negative electrode of a power source, a drain of the driving transistor is connected to the cathode of the light emitting unit;
- wherein a gate of the data write-in transistor is connected to a write-in signal input end, a source of the data write-in transistor is connected to a data signal input end, and a drain of the data write-in transistor is connected to a second node;
- wherein a gate of the reset transistor is connected to a reset signal input end, a source of the reset transistor is connected to a reference signal input end, and a drain of the reset transistor is connected to the second node;
- wherein a gate of the compensation transistor is connected to a reset signal input end, a source of the compensation transistor is connected to a positive electrode of the power source, and a drain of the compensation transistor is connected to the first node;
- and
- wherein a first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the second node,
- wherein during a first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned on;
- wherein during a second period after the first period, the reset transistor and the compensation transistor are turned on, the data write-in transistor is turned off, and the driving transistor is turned off;
- wherein during a third period after the second period, the reset transistor, the compensation transistor, the data write-in transistor and the driving transistor are all turned off;
- wherein during a fourth period after the third period, the driving transistor and the data write-in transistor are turned on, and the compensation transistor and the reset transistor are turned off;
- wherein during a fifth period after the fourth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off;
- and
- wherein during a sixth period after the fifth period, the driving transistor is turned on, the data write-in transistor, the compensation transistor and the reset transistor are turned off.
13 more elements
Dependencies are inferred from the claim text.