US 12,008,945 B1Granted

Tiling display apparatus and output synchronization method thereof

AssigneeLG Display Co., Ltd.

InventorsSang Woo Park, Tae Gung Kim

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Abstract

A tiling display apparatus comprises: a first display group including first timing controllers to receive a first input data enable signal from a first system chip, the first input data enable signal having a first delay; and a second display group including second timing controllers to receive a second input data enable signal from a second system chip, the second input data enable signal having a second delay, wherein the first timing controllers of the first display group and the second timing controllers of the second display group share input delay information about the first delay of the first input data enable signal and input delay information about the second delay of the second input data enable signal with each other, and each of the first timing controllers and the second timing controllers generate a common output data enable signal based on the shared input delay information.

Claims19

Dependent claims

A tiling display apparatus comprising:

a first display group including first timing controllers configured to receive a first input data enable signal that is synchronized with a first input image from a first system chip, the first input data enable signal having a first delay;
and
a second display group including second timing controllers configured to receive a second input data enable signal that is synchronized with a second input image from a second system chip, the second input data enable signal having a second delay that is different from the first delay,
wherein the first timing controllers of the first display group and the second timing controllers of the second display group share input delay information about the first delay of the first input data enable signal and input delay information about the second delay of the second input data enable signal with each other, and each of the first timing controllers and the second timing controllers generate a common output data enable signal based on the input delay information about the first delay and the input delay information about the second delay, and
wherein an output timing of the first input image to display the first input image matches an output timing of the second input image to display the second input image based on the common output data enable signal generated by each of the first timing controllers and the second timing controllers.

2 more elements

A tiling display device comprising:

a plurality of system chips configured to output a plurality of input data enable signals having different delays, each of the plurality of input data enable signals synchronized with a corresponding portion of an input image;
and
a plurality of display groups that are each configured to receive a corresponding input data enable signal from the plurality of input data enable signals and display a corresponding portion of the input image, each of the plurality of display groups including a plurality of timing controllers that are each configured to:
receive delay information indicative of different delays of the plurality of input data enable signals from one or more other timing controllers from the plurality of timing controllers;
determine a longest delay of the different delays from the received delay information;
and
generate a corresponding output data enable signal based on the longest delay, the corresponding output data enable signal indicative of when the display group displays the corresponding portion of the input image,
wherein output data enable signals generated by the plurality of timing controllers have a same timing at which each of the plurality of display groups displays the corresponding portion of the image.

5 more elements

A tiling display device comprising:

a plurality of system chips configured to output a plurality of input data enable signals having different delays, each of the plurality of input data enable signals synchronized with a corresponding portion of an input image;
a plurality of display groups arranged in a plurality of rows of display groups, each display group including a plurality of timing controllers;
a plurality of first interfaces configured to receive the plurality of input data enable signals, each first interface configured to connect together the plurality of timing controllers included in a corresponding display group from the plurality of display groups and connect one timing controller from the plurality of timing controllers included in the corresponding display group to a corresponding one of the plurality of system chips;
and
a second interface configured to connect together the plurality of timing controllers across all of the plurality of display groups.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/226,546Filed 26 Jul 2023
Priority: KR 10-2022-019100230 Dec 2022
Published: US 2024/0221593 A14 Jul 2024
Granted: 11 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G09G 3/2096
Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces…:…
G09G 3/32
Using electroluminescent panels: semiconductive, e.g. using light-emitting diodes [LED]
G09G 2300/026
Composition of display devices: video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
G09G 2300/0452
Pixel structures: details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components

Family

US 2024/0221593 A1Published application
US 12,008,945 B1This patent

From the US filing history. Foreign family members aren’t listed.

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Citations

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