Back to results
US 12,008,938 B2Granted
Display device with clock control chip and data driving chip for adjusting a phase of clock signal output
AssigneeTcl China Star Optoelectronics Technology Co., Ltd.
InventorJinfeng Liu
Life of this patent
Estimating the term…
Abstract
A display device is provided. The display device includes a clock control chip configured to transmit display signals and a data driving chip connected to the clock control chip. The data driving chip is configured to adjust a phase of the clock signal output by the data driving chip based on the display signal.
Claims9
A display device comprising:
- a clock control chip configured to transmit display signals;
- and
- a data driving chip connected to the clock control chip, wherein the data driving chip is configured to adjust a phase of a clock signal output by the data driving chip based on the display signals,
- wherein the data driving chip comprises a clock generation module, a frequency confirmation module, a code type detection module, and an output control module, the clock generation module is connected to the frequency confirmation module, and the clock generation module and the code type detection module are both connected to the output control module;
- wherein the clock generation module is configured to generate an initial clock signal and comprises:
- a first clock output terminal, wherein the first clock output terminal is connected to the frequency confirmation module, and the clock generation module outputs the initial clock signal to the frequency confirmation module through the first clock output terminal;
- a second clock output terminal, wherein the second clock output terminal is connected to the output control module, and the clock generation module outputs the adjusted initial clock signal to the output control module through the second clock output terminal;
- and a feedback input terminal, wherein the feedback input terminal is connected to the frequency confirmation module, and the clock generation module receives the feedback signal through the feedback input terminal;
- wherein the frequency confirmation module is configured to receive the display signal and the initial clock signal, and output a feedback signal to the clock generation module based on the display signal and the initial clock signal to control the clock generation module to adjust frequency of the initial clock signal and to output an adjusted initial clock signal to the output control module, and comprises:
- a first frequency confirmation input terminal, wherein the first frequency confirmation input terminal is connected to the clock generation module, and the frequency confirmation module receives the initial clock signal through the first frequency confirmation input terminal;
- a second frequency confirmation input terminal, wherein the second frequency confirmation input terminal is connected to the clock control chip, and the frequency confirmation module receives the display signal through the second frequency confirmation input terminal;
- and a feedback output terminal wherein the feedback output terminal is connected to the clock generation module, and the frequency confirmation module outputs the feedback signal through the feedback output terminal;
- wherein the code type detection module is configured to receive the display signal, obtain phase alignment starting point information based on the display signal, and output the phase alignment starting point information to the output control module, and comprises:
- a code type confirmation input terminal, wherein the code type confirmation input terminal is connected to the clock control chip, and the code type detection module receives the display signal through the code type confirmation input terminal;
- and a code type confirmation output terminal, wherein the code type confirmation output terminal is connected to the output control module, and the code type detection module outputs the phase alignment starting point information through the code type confirmation output terminal;
- and
- wherein the output control module is configured to output the clock signal based on the adjusted initial clock signal and the phase alignment starting point information, and comprises:
- a first input terminal, wherein the first input terminal is connected to the clock generation module, and the output control module receives the adjusted initial clock signal through the first input terminal;
- a second input terminal, wherein the second input terminal is connected to the code type detection module, and the output control module receives the phase alignment starting point information through the second input terminal;
- and an output terminal, wherein the output control module outputs the clock signal through the output terminal.
17 more elements
A display device, comprising:
- a clock control chip configured to transmit display signals;
- and
- a data driving chip connected to the clock control chip, wherein the data driving chip is configured to adjust a phase of a clock signal output by the data driving chip based on the display signals;
- the data driving chip comprises a clock generation module, a frequency confirmation module, a code type detection module, and an output control module, the clock generation module is connected to the frequency confirmation module, and the clock generation module and the code type detection module are both connected to the output control module;
- wherein the clock generation module is configured to generate an initial clock signal, and comprises:
- a first clock output terminal, wherein the first clock output terminal is connected to the frequency confirmation module, and the clock generation module outputs the initial clock signal to the frequency confirmation module through the first clock output terminal;
- a second clock output terminal, wherein the second clock output terminal is connected to the output control module, and the clock generation module outputs the adjusted initial clock signal to the output control module through the second clock output terminal;
- and a feedback input terminal, wherein the feedback input terminal is connected to the frequency confirmation module, and the clock generation module receives the feedback signal through the feedback input terminal;
- wherein the frequency confirmation module is configured to receive the display signal and the initial clock signal, and output a feedback signal to the clock generation module based on the display signal and the initial clock signal to control the clock generation module to adjust frequency of the initial clock signal and to output an adjusted initial clock signal to the output control module, and comprises:
- a first frequency confirmation input terminal, wherein the first frequency confirmation input terminal is connected to the clock generation module, and the frequency confirmation module receives the initial clock signal through the first frequency confirmation input terminal;
- a second frequency confirmation input terminal, wherein the second frequency confirmation input terminal is connected to the clock control chip, and the frequency confirmation module receives the display signal through the second frequency confirmation input terminal;
- and a feedback output terminal wherein the feedback output terminal is connected to the clock generation module, and the frequency confirmation module outputs the feedback signal through the feedback output terminal;
- wherein the code type detection module is configured to receive the display signal, obtain phase alignment starting point information based on the display signal, and output the phase alignment starting point information to the output control module, and comprises:
- a code type confirmation input terminal, wherein the code type confirmation input terminal is connected to the clock control chip, and the code type detection module receives the display signal through the code type confirmation input terminal;
- and a code type confirmation output terminal, wherein the code type confirmation output terminal is connected to the output control module, and the code type detection module outputs the phase alignment starting point information through the code type confirmation output terminal;
- wherein the output control module is configured to output the clock signal based on the adjusted initial clock signal and the phase alignment starting point information, and comprises:
- a first input terminal, wherein the first input terminal is connected to the clock generation module, and the output control module receives the adjusted initial clock signal through the first input terminal;
- a second input terminal, wherein the second input terminal is connected to the code type detection module, and the output control module receives the phase alignment starting point information through the second input terminal;
- and an output terminal, wherein the output control module outputs the clock signal through the output terminal;
- and
- wherein the phase alignment starting point information comprises a rising edge starting point or a falling edge starting point.
18 more elements
Dependencies are inferred from the claim text.