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US 12,008,460 B2Granted
Performing processing-in-memory operations related to pre-synaptic spike signals, and related methods and systems
AssigneeMicron Technology, Inc.
InventorsDmitri Yudanov, Sean S. Eilert, Hernan A. Castro, Ameen D. Akel
Life of this patent
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Abstract
Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.
Claims22
A system, comprising:
- a memory array comprising a number of memory cells at intersections of a number of word lines and a number of bit lines, wherein data written to the number of memory cells corresponds to synaptic weights values;
- a driver configured to drive the number of word lines;
- and
- circuitry comprising a sense amplifier coupled to the number of bit lines and configured to generate a spike signal of a neuron, the circuitry configured to:
- receive output signals from the number of bit lines;
- in response to a first signal driven on a word line of the number of word lines before generation of the spike signal of the neuron, generate a second signal with a voltage, current, or timing characteristic, or combination thereof that increases a conductance of a first memory cell of the number of memory cells according to a spike timing dependent plasticity (STDP) characteristic of the first memory cell;
- in response to the first signal driven on the word line after the generation of the spike signal of the neuron, generate a third signal with a different voltage, current, or timing characteristic, or combination thereof that decreases the conductance of the first memory cell according to the STDP characteristic;
- and
- in response to the first signal driven on the word line:
- integrate current on a first bit line of the number of bit lines intersecting—
- enable threshold modulation on a second bit line of the number of bit lines intersecting the word line.
8 more elements
A method, comprising:
- driving a first signal on a word line;
- in response to the first signal driven on the word line before generation of a spike signal of a neuron:
- generating, via circuitry configured to generate the spike signal, a second signal with a voltage, current, or timing characteristic, or combination thereof that increases a conductance of a memory cell in a long-term potentiation (LTP) window of a spike timing dependent plasticity (STDP) characteristic;
- and
- transmitting the second signal to a bit line in response to the generation of a spike signal of a neuron, wherein the memory cell is coupled to the word line and the bit line;
- in response to the first signal driven on the word line after the generation of the spike signal of the neuron:
- generating, via the circuitry configured to generate the spike signal, a third signal with a different voltage, current, or timing characteristic, or combination thereof that decreases the conductance of the memory cell in a long-term depression (LTD) window according to the STDP characteristic;
- and
- transmitting the third signal to the bit line;
- and
- in response to the generation of the spike signal of the neuron driven on the bit line, transmit a feedback signal from the circuitry to each of a plurality of memory cells on the bit line, wherein the feedback signal is a decaying bias.
8 more elements
An electronic system, comprising:
- at least one input device;
- at least one output device;
- at least one processor device operably coupled to the input device and the output device;
- and
- at least one memory device operably coupled to the at least one processor device and comprising:
- a memory array comprising a number of memory cells at intersections of a number of word lines and a number of bit lines, wherein data written to the number of memory cells correspond to synaptic weight values;
- circuitry comprising a sense amplifier coupled to the number of bit lines and configured to generate a spike signal of a neuron, the circuitry configured to:
- generate, in response to a first signal driven on a word line of the number of word lines before generation of the spike signal of the neuron, a second signal with a voltage, current, or timing characteristic, or combination thereof that increases a conductance of a memory cell of the number of memory cells;
- generate, in response to the first signal driven on the word line after the generation of the spike signal of the neuron, a third signal with a different voltage, current, or timing characteristic, or combination thereof that decreases a conductance of the memory cell;
- and
- in response to the generation of the spike signal of the neuron driven on a bit line of the number of bit lines, transmit a feedback signal from the sense amplifier to each of a plurality of memory cells on the bit line, wherein the feedback signal is a decaying bias.
8 more elements
Dependencies are inferred from the claim text.