Hardware directed core parking based on performance and energy efficiency capabilities of processing units and runtime system characteristics

A semiconductor apparatus comprising:

• one or more substrates;
• and
• logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
• determine a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis;
• determine a runtime energy efficiency of the plurality of heterogeneous processing units based on the system-level thread characteristics, wherein the runtime energy efficiency is determined on a per efficiency class basis;
• and
• selectively unpark one or more of the plurality of heterogeneous processing units based on the runtime performance and the runtime energy efficiency,
• wherein to selectively unpark one or more of the plurality of heterogeneous processing units based on the runtime performance, the logic coupled to the one or more substrates is to:
• selectively unpark one or more processing units in a first performance class, and
• maintain one or more processing units in a second performance class in a parked state, wherein a first runtime performance associated with the first performance class is to differ from a second runtime performance associated with the second performance class,
• wherein to selectively unpark one or more processing units in the first performance class, the logic coupled to the one or more substrates is to:
• selectively unpark a first subset of processing units in the first performance class based on one or more parking hints, and
• maintain a second subset of processing units in the first performance class in the parked state based on the one or more parking hints,
• wherein the one or more parking hints include a preference to unpark a next performant core by increasing a performance delta between subsequent processing units.

At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:

• determine a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis;
• determine a runtime energy efficiency of the plurality of heterogeneous processing units based on the system-level thread characteristics, wherein the runtime energy efficiency is determined on a per efficiency class basis;
• and
• selectively unpark one or more of the plurality of heterogeneous processing units based on the runtime performance and the runtime energy efficiency,
• wherein to selectively unpark one or more of the plurality of heterogeneous processing units based on the runtime performance, the instructions, when executed, cause the computing system to:
• selectively unpark one or more processing units in a first performance class, and
• maintain one or more processing units in a second performance class in a parked state, wherein a first runtime performance associated with the first performance class is to differ from a second runtime performance associated with the second performance class,
• wherein to selectively unpark one or more processing units in the first performance class, the instructions, when executed, cause the computing system to:
• selectively unpark a first subset of processing units in the first performance class based on one or more parking hints, and
• maintain a second subset of processing units in the first performance class in the parked state based on the one or more parking hints,
• wherein the one or more parking hints include a preference to unpark a next performant core by increasing a performance delta between subsequent processing units.

A method comprising:

• determining a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis;
• determining a runtime energy efficiency of the plurality of heterogeneous processing units based on the system-level thread characteristics, wherein the runtime energy efficiency is determined on a per efficiency class basis;
• and
• selectively unparking one or more of the plurality of heterogeneous processing units based on the runtime performance and the runtime energy efficiency,
• wherein selectively unparking one or more of the plurality of heterogeneous processing units based on the runtime performance includes:
• selectively unparking one or more processing units in a first performance class, and
• maintaining one or more processing units in a second performance class in a parked state, wherein a first runtime performance associated with the first performance class differs from a second runtime performance associated with the second performance class,
• wherein selectively unparking one or more processing units in the first performance class includes:
• selectively unparking a first subset of processing units in the first performance class based on one or more parking hints, and
• maintaining a second subset of processing units in the first performance class in the parked state based on the one or more parking hints,
• wherein the one or more parking hints include a preference to unpark a next performant core by increasing a performance delta between subsequent processing units.