US 12,008,377 B2 · SIMD operand permutation with selection from among multiple registers

Abstract

Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.

Claims20

Dependent claims

An apparatus, comprising:

a graphics processor that includes:
first storage circuitry configured to store multiple thread-specific versions of a first register for a threads of a single-instruction multiple-data (SIMD) group;
second storage circuitry configured to store multiple thread-specific versions of a second register for the threads of the SIMD group;
third storage circuitry configured to store multiple thread-specific versions of a third register for threads of the SIMD group;
and
a set of multiple hardware pipelines configured to:
execute, using routing circuitry, an instruction to:
store a proper subset of the thread-specific versions of the first register from the first storage circuitry in thread-specific versions of the third register in the third storage circuitry;
and
store a proper subset of the thread-specific versions of the second register from the second storage circuitry in thread-specific versions of the third register in the third storage circuitry;
wherein the storage of the proper subsets stores values that are based on thread-specific versions of the first and second registers to other threads' versions of the third register for the SIMD group.

8 more elements

Dependencies are inferred from the claim text.

SIMD operand permutation with selection from among multiple registers

Life of this patent

SIMD operand permutation with selection from among multiple registers

Life of this patent

Abstract

Claims20