Memory device including interface circuit and method of operating the same

A memory system comprising:

• a memory controller configured to receive a first clock and a read command from a host device, transmit a first control signal or a second control signal to an interface circuit, transmit read data according to the first clock to the host device;
• and
• a memory device including a first NVM, a second NVM, and the interface circuit which is connecting between the memory controller and the first NVM and the second NVM,
• wherein the interface circuit is configured to:
• in response to receiving the first control signal from the memory controller, generate and transmit, a second clock which is divided from the first clock based on a number of NVMs, to each of the first NVM and the second NVM,
• in response to receiving the second control signal from the memory controller, transmit the first clock received from the memory controller to the first NVM and the second NVM,
• receive, at a first time, a first data strobe signal generated by the first NVM,
• receive, at a second time, a second data strobe signal generated by the second NVM,
• identify a skew based on the first time and the second time, and
• generate and transmit, to the memory controller, the read data by combining first divided read data from the first NVM and second divided read data from the second NVM based on the skew, and
• wherein the memory controller is configured to transmit one of the first control signal and the second control signal, to the interface circuit, based on a value of the first clock.

An operating method of a memory device including a first NVM, a second NVM and an interface circuit connected to each of the first NVM and the second NVM, the method comprising:

• receiving, by the interface circuit, a first clock signal;
• in response to receiving a first control signal from a memory controller, generating and transmitting, by the interface circuit, a second clock signal, which is divided from the first clock signal based on a number of NVMs, to each of the first NVM and the second NVM;
• in response to receiving a second control signal from the memory controller, transmitting, by the interface circuit, the first clock received from the memory controller to the first NVM and the second NVM;
• receiving, by the interface circuit at a first time, a first data strobe signal generated by the first NVM in response to the first NVM receiving of the second clock signal from the interface circuit;
• receiving, by the interface circuit at a second time, a second data strobe signal generated by the second NVM in response to the second NVM receiving of the second clock signal from the interface circuit;
• identifying, by the interface circuit, a skew based on the first time and the second time;
• and
• generating and transmitting, to the memory controller, read data by combining first divided read data from the first NVM and second divided read data from the second NVM based on the skew, and
• wherein the interface circuit is configured to receive one of the first control signal and the second control signal from the memory controller based on a value of the first clock.