Memory system

A memory system comprising:

• a nonvolatile memory;
• a memory bus that includes a plurality of data lines;
• and
• a controller that includes an encoder configured to encode a first group of data including a plurality of first data, each first data having a plurality of bits, and is configured to transmit the encoded first group of data to the nonvolatile memory via the data lines,
• wherein the encoder is configured to perform a first encoding process of generating a second group of data including a plurality of second data from the plurality of first data in the first group, and a second encoding process of generating a third group of data including a plurality of third data from the plurality of second data in the second group, each of the second data and each of the third data having the same number of bits as the first data, and
• in the first encoding process, for each first data in the first group:
• if the number of bits of the first data having a first logical value is greater than or equal to the number of bits of the first data having a second logical value, each bit of the second data has the same logical value as a corresponding bit of the first data;
• and
• if the number of bits of the first data having the first logical value is less than the number of bits of the first data having the second logical value, each bit of the second data has an inverted logical value of the corresponding bit of the first data, and
• wherein the second logical value is less likely to be the value in an n-th bit position of the plurality of third data in the third group than the value in any of the bit positions of the plurality of second data in the second group.