Reducing index update messages for memory-based communication queues
AssigneeMicron Technology, Inc.
InventorsMichael Keith Dugan, Tony M. Brewer
Life of this patent
Estimating the term…
Abstract
A system includes a host device, a memory device, and a command manager configured to reorder respective command responses for corresponding commands between the host device and the memory device. The command manager is further configured to receive a command response associated with a transaction identifier for each command. An index value for the command is written to a reordering queue. In response to a command response write for the command response, the index value from the reordering queue is read. The index value is written in an index update queue. A network write index update message is transmitted.
Claims20
A system, comprising:
- a host device;
- a memory device;
- and
- a command manager configured to reorder respective command responses for corresponding commands between the host device and the memory device, the command manager is further configured to:
- receive a command response associated with a transaction identifier for each command;
- write an index value for the command to a reordering queue;
- and
- in response to a command response write for the command response:
- read the index value from the reordering queue;
- write the index value to an index update queue;
- and
- transmit a network write index update message.
A method, comprising:
- for each command of a plurality of commands, receiving a command response associated with a transaction identifier;
- writing an index value for the command response to a reordering queue;
- and
- in response to a command response write for the command response:
- reading the index value from the reordering queue;
- writing the index value to an index update queue based on a temporal order that the command response was received;
- and
- transmitting a network write index update message for the command response.
At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processor circuit of a memory system, cause the processor circuit to perform operations comprising:
- for each command of a plurality of commands, receiving a command response associated with a transaction identifier;
- writing an index value for the command response to a reordering queue;
- and
- in response to a command response write for the command response:
- reading the index value from the reordering queue and;
- writing the index value to an index update queue based on a temporal order that the command response was received;
- and
- transmitting a network write index update message for the command response.
Dependencies are inferred from the claim text.