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US 12,008,236 B2Granted
Tuned datapath in stacked memory device
AssigneeMicron Technology, Inc.
InventorsHari Giduturi, Bret Addison Johnson
Life of this patent
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Abstract
A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.
Claims18
A device, comprising:
- a first memory die;
- a second memory die directly coupled to the first memory die via a first bus;
- and
- a second bus directly coupled to the first memory die and indirectly coupled to the second memory die, wherein the first memory die comprises a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, wherein the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value, wherein the first memory die comprises a self tuning circuit that when in operation controls configuration of the second trim circuit of the second memory die.
1 more element
A method, comprising:
- initiating a memory operation at a first memory die of a memory stack via a front end interface path directly coupled to the first memory die;
- determining a first amount of time to complete the memory operation;
- initiating the memory operation at a second memory die of the memory stack via the front end interface path indirectly coupled to the second memory die;
- determining a second amount of time to complete the memory operation;
- calibrating a first delay circuit of the first memory die to generate a first signal transmission delay in the first memory die when the first amount of time is less than the second amount of time;
- and
- calibrating a second delay circuit of the second memory die via a self tuning circuit disposed in the first memory die to generate a second signal transmission delay in the second memory die when the first amount of time is greater than the second amount of time.
4 more elements
A device, comprising:
- a first memory die comprising a first trim circuit that when in operation delays transmission of a signal by the first memory die by a first fixed amount, wherein the first memory die when in operation receives first operational signals from an external host directly coupled to the first memory die via a front end interface path;
- and
- a second memory die disposed directly on the first memory die, wherein the second memory die when in operation receives second operational signals indirectly from the external host via a direct coupling between the first memory die and the second die, wherein the direct coupling between the first memory die and the second die is separate from the front end interface path directly coupling the first memory die and the external host, wherein the second memory die comprises a second trim circuit that when in operation delays transmission of a second signal by the second memory die by a second fixed amount, wherein the first fixed amount and the second fixed amount equalize an amount of time used by the first memory die and the second memory die to complete a memory operation, wherein the first memory die comprises a self tuning circuit that when in operation calibrates the first trim circuit to delay transmission of the signal by the first memory die by the first fixed amount and when in operation calibrates the second trim circuit to delay transmission of the second signal by the second memory die by the second fixed amount.
Dependencies are inferred from the claim text.