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US 12,008,234 B2Granted
Managing memory in an electronic system
AssigneeTeradyne, Inc.
InventorsScott D. Schaber, Howard Lin
Life of this patent
Estimating the term…
Abstract
An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.
Claims26
A system comprising:
- first memory;
- second memory having a greater storage capacity than the first memory;
- and
- a logic circuit configured to move test data from the second memory to the first memory while (i) reading other test data from the first memory, or (ii) both reading the other test data and processing the other test data, the logic circuit being configured to process the other test data prior to output along a test channel, where the test channel leads to a device under test (DUT) to be tested;
- wherein the first memory comprises a first memory module and a second memory module;
- and
- wherein moving the test data from the second memory to the first memory comprises reading the test data from the second memory and storing the test data, in the first memory module while reading the other test data from the second memory module.
4 more elements
A system comprising:
- first memory;
- second memory having a greater storage capacity than the first memory;
- and
- a logic circuit configured to move test data from the second memory to the first memory while (i) reading other test data from the first memory, (ii) processing the other test data, or (iii) both reading the other test data and processing the other test data, the logic circuit being configured to process the other test data prior to output along a test channel, where the test channel leads to a device under test (DUT) to be tested;
- wherein the first memory stores expect data, the expect data representing expected DUT test results;
- and
- wherein the logic circuit is configured to receive test result data associated with the DUT, to read the expect data from the first memory, to compare the test result data to the expect data to identify whether the DUT has passed or failed testing, and to store in memory information for the DUT based on comparing the test result data to the expect data.
4 more elements
A system comprising:
- first memory;
- second memory having a greater areal density than the first memory;
- and
- a logic circuit configured to perform operations comprising:
- reading first data from the second memory;
- storing the first data in the first memory;
- reading the first data from the first memory;
- processing the first data prior to output to a test channel, where the test channel leads to a device under test (DUT) to be tested;
- and
- while reading the first data from the first memory or while processing the first data:
- (i) reading second data from the second memory, and (ii) storing the second data in available first memory;
- wherein the first data and the second data comprise test data;
- wherein the first memory comprises a first memory module and a second memory module;
- wherein storing the first data in the first memory comprises storing the first data in the first memory module;
- wherein reading the first data from the first memory comprises reading the first data from the first memory module;
- and
- wherein storing the second data in available first memory comprises storing the second data in the second memory module, the second memory module comprising the available first memory.
14 more elements
A system comprising:
- first memory;
- second memory having a greater areal density than the first memory;
- and
- a logic circuit configured to perform operations comprising:
- reading first data from the second memory;
- storing the first data in the first memory;
- reading the first data from the first memory;
- processing the first data prior to output to a test channel, where the test channel leads to a device under test (DUT) to be tested;
- and
- while reading the first data from the first memory or while processing the first data:
- (i) reading second data from the second memory, and (ii) storing the second data in available first memory;
- wherein the first data and the second data comprise test data;
- wherein the first memory stores expect data, the expect data representing expected DUT test results;
- and
- wherein the operations further comprise:
- receiving test result data for the DUT;
- reading the expect data from the first memory;
- comparing the test result data to the expect data to identify whether the DUT passed or failed testing;
- and
- storing, in the first memory, information for the DUT based on comparing the test result data to the expect data.
17 more elements
One or more non-transitory machine-readable devices storing instructions that are executable by one or more processing devices to perform operations in a system that comprises first memory and second memory having a greater areal density than the first memory, the operations comprising:
- reading first data from the second memory;
- storing the first data in the first memory;
- reading the first data from the first memory;
- processing the first data prior to output to a test channel, where the test channel leads to a device under test (DUT) to be tested;
- and
- while reading the first data read from the first memory or while processing the first data:
- (i) reading second data from the second memory, and (ii) storing the second data in available first memory;
- wherein the first data and the second data comprise test data;
- wherein the first memory stores expect data, the expect data representing expected DUT test results;
- and
- wherein the operations further comprise:
- receiving test result data for the DUT;
- reading the expect data from the first memory;
- comparing the test result data to the expect data to identify whether the DUT has passed or failed testing;
- and
- storing, in the first memory, information for the DUT based on comparing the test result data to the expect data.
13 more elements
A test system comprising:
- first memory;
- second memory having a greater storage capacity than the first memory and having a greater latency that the first memory;
- and
- a logic circuit configured to store test data in the second memory and configured to copy at least part of the test data stored in the second memory into the first memory for execution by one or more processing devices, the test data comprising test vectors for testing a device under test (DUT);
- wherein the first memory stores expect data, the expect data representing expected DUT test results;
- and
- wherein the logic circuit is configured to receive test result data associated with the DUT, to read the expect data from the first memory, to compare the test result data to the expect data to identify whether the DUT has passed or failed testing, and to store in memory information for the DUT based on comparing the test result data to the expect data.
4 more elements
A test system comprising:
- first memory;
- second memory having a greater storage capacity than the first memory and having a greater latency that, the first memory;
- and
- a logic circuit configured to store test data in the second memory and configured to copy at least a first part of the test data stored in the second memory into the first memory for execution by one or more processing devices, the test data comprising test vectors for testing a device;
- wherein the second memory comprises one terabyte (TB) or more of storage and the first memory comprises 32 gigabytes or less of storage.
2 more elements
Dependencies are inferred from the claim text.