Multi-mode architecture for unifying matrix multiplication, 1×1 convolution and 3×3 convolution

A method, comprising:

• communicating data from a first memory to first, second and third processing elements;
• selecting, by a controller, one of a first or second configuration of an integrated circuit for transmitting data from a second memory to the first, second and third processing elements, the integrated circuit being controllable to operate in the first configuration and being controllable to operate in the second configuration, wherein:
• in the first configuration, first, second and third groups of values from the second memory are transmitted to the first, second and third processing elements, respectively, and three values are shared between the first, second and third groups of values from the second memory, and
• in the second configuration, fourth, fifth and sixth groups of values from the second memory are transmitted to the first, second and third processing elements, respectively;
• communicating data from the second memory to the first, second and third processing elements in the selected configuration of the integrated circuit;
• manipulating, by the first processing element, the data from the first memory with the first or fourth groups of values from the second memory so as to compute a first dot product;
• manipulating, by the second processing element, the data from the first memory with the second or fifth groups of values from the second memory so as to compute a second dot product;
• and
• manipulating, by the third processing element, the data from the first memory with the third or sixth groups of values from the second memory so as to compute a third dot product.