Low-latency optical connection for CXL for a server CPU

A processor system on a chip (SOC), comprising:

• one or more central processing units (CPUs) comprising multiple cores;
• a dual Compute Express Link (CXL) communication path comprising:
• an electrical communication path incorporating a logical electrical CXL protocol stack having multiple levels including a protocol layer, a transaction layer, a link layer, a MAC layer, a PHY layer, and a physical channel to transmit and receive an electrical bit stream;
• and
• an optical CXL communication path incorporating a logical optical CXL protocol stack path that transmits and receives an optical bit stream directly after the link layer, bypassing several levels of the logical electrical CXL protocol stack;
• a multiplexer to direct data frames to either the electrical communication path or the optical CXL communication path;
• and
• at least one CXL device connected to the dual CXL communication path.

A method of fabricating a processor system on a chip (SOC), the method comprising:

• fabricating one or more central processing units (CPUs) comprising multiple cores;
• fabricating a dual Compute Express Link (CXL) communication path comprising:
• an electrical communication path incorporating a logical electrical CXL protocol stack having multiple levels including a protocol layer, a transaction layer, a link layer, a MAC layer, a PHY layer, and a physical channel to transmit and receive an electrical bit stream;
• and
• an optical CXL communication path incorporating a logical optical CXL protocol stack path that transmits and receives an optical bit stream directly after the link layer, bypassing several levels of the logical electrical CXL protocol stack;
• connecting a multiplexer to the optical CXL communication path to direct data frames to either select the electrical communication path or the optical CXL communication path.