Direct data transfer system

System comprising:

• a processor;
• a circuit of direct transfer of a data sequence between a source memory circuit and a destination memory circuit without transiting through the processor, a sub-region of the source memory circuit comprising a sequence of consecutive locations in terms of addressing containing the elements of a data array, wherein the direct transfer circuit is adapted to receiving and decoding computing kernel information called BIT_PATTERN of an elementary data pattern to be transferred defined from an elementary array of k*1 binary elements, with k an integer greater than or equal to 2 and 1 an integer greater than or equal to 2, the size of said elementary array being smaller than the size of said data array, the elementary array being intended to identify an elementary array window of said array, each element of the elementary array comprising a bit capable of taking a first or a second state according respectively to whether the element does not belong or belongs to said pattern, the elementary array of the BIT_PATTERN comprising a reference element;
• the direct transfer circuit receiving a source address for a first pattern to be transferred, this source address corresponding to the address in said sub-region of said reference element of the BIT_PATTERN and corresponding to a reference piece of data of said data array located at this source address, the other elements of the BIT_PATTERN being associated with other data of said array by relative positioning with respect to, respectively, the reference element of the BIT_PATTERN and the reference piece of data of said array;
• the direct transfer circuit being adapted, during the execution of the transfer of an elementary pattern, to recovering the data of said array associated with elements of the BIT_PATTERN having their bit in said second state.