Victim cache with write miss merging
AssigneeTexas Instruments Incorporated
InventorsNaveen Bhoria, Timothy David Anderson, Pete Hippleheuser
Life of this patent
Estimating the term…
Abstract
A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.
Claims20
A system comprising:
- a processor;
- a main cache;
- a victim cache coupled to the main cache;
- and
- a cache controller coupled to the processor, the main cache, and the victim cache and configured to:
- receive, from the processor, a write command associated with a memory location and a set of data;
- determine whether the write command is associated with a hit in the main cache or the victim cache;
- and
- based on the write command not being associated with a hit in the main cache and the victim cache, store the set of data in the victim cache.
A method comprising:
- receiving a write command associated with a memory location and a set of data;
- determining, based on the memory location, whether the write command is associated with a hit in a main cache or a victim cache;
- and
- based on the write command not being associated with a hit in the main cache and the victim cache, storing the set of data in the victim cache.
Dependencies are inferred from the claim text.