Memory cache with partial cache line valid states

An apparatus, comprising:

• a cache memory circuit configured to store a plurality of cache lines that include a plurality of entries;
• a cache controller circuit configured to:
• receive a write request to an address associated with a particular cache line, wherein the write request includes new values for a proper subset of entries in the particular cache line;
• and
• in response to a determination that a status of the particular cache line indicates that at least a first portion of the particular cache line is invalid and at least a second portion of the particular cache line is modified relative to memory locations at the associated address in a memory:
• retrieve a mask value that indicates valid and invalid entries of the particular cache line;
• store the new values in the proper subset of entries;
• and
• update the mask value based on the store to the proper subset of entries;
• determine, using the updated mask value, whether any entry in the particular cache line remains invalid after the storing;
• and
• in response to a determination that none of the entries are invalid:
• update the status of the particular cache line to indicate all the entries of the particular cache line are valid;
• and
• discard the updated mask value.

An apparatus, comprising:

• a cache memory circuit configured to store a plurality of cache lines that include a plurality of entries;
• a cache controller circuit configured to:
• receive a write request to an address associated with a particular cache line, wherein the write request includes new values for a proper subset of entries in the particular cache line;
• and
• in response to a determination that a status of the particular cache line indicates that at least a first portion of the particular cache line is invalid and at least a second portion of the particular cache line is modified relative to memory locations at the associated address in a memory:
• retrieve a mask value that indicates valid and invalid entries of the particular cache line;
• store the new values in the proper subset of entries;
• and
• update the mask value based on the store to the proper subset of entries;
• receive a notification that values for memory locations in the memory that correspond to one or more of the entries of the particular cache line have been modified outside of the cache memory circuit;
• and
• update the mask value based on the notification.

A method comprising:

• setting, by a cache controller circuit coupled to a cache memory circuit, a value in a cache tag associated with a particular cache line to indicate a partial state, the partial state indicative of an invalid first portion and a modified second portion of the particular cache line;
• receiving, by the cache controller circuit, a partial write request for an address associated with the particular cache line, wherein the partial write request includes new values for a proper subset of entries in the particular cache line;
• storing, by the cache controller circuit, valid values of the partial write request in corresponding entries of the particular cache line without modifying remaining entries in the particular cache line;
• sending, by the cache controller circuit, a request to a memory circuit to store the new values in the proper subset of entries of the particular cache line to locations in the memory circuit corresponding to the address;
• in response to the cache tag indicating the partial state, accessing, by the cache controller circuit, a mask value that identifies entries of the invalid first portion;
• and
• updating, by the cache controller circuit, the mask value based on the storing.

A method comprising:

• setting, by a cache controller circuit coupled to a cache memory circuit, a value in a cache tag associated with a particular cache line to indicate a partial state, the partial state indicative of an invalid first portion and a modified second portion of the particular cache line;
• receiving, by the cache controller circuit, a partial write request for an address associated with the particular cache line, wherein the partial write request includes new values for a proper subset of entries in the particular cache line;
• storing, by the cache controller circuit, valid values of the partial write request in corresponding entries of the particular cache line without modifying remaining entries in the particular cache line;
• in response to the cache tag indicating the partial state, accessing, by the cache controller circuit, a mask value that identifies entries of the invalid first portion;
• update the mask value based on the store to the proper subset of entries;
• determining, by the cache controller circuit using the updated mask value, that all of the entries of the particular cache line are valid;
• updating, by the cache controller circuit, the value in the cache tag to indicate that all the entries are valid;
• and
• invalidating, by the cache controller circuit, the updated mask value.

A method comprising:

• setting, by a cache controller circuit coupled to a cache memory circuit, a value in a cache tag associated with a particular cache line to indicate a partial state, the partial state indicative of an invalid first portion and a modified second portion of the particular cache line;
• receiving, by the cache controller circuit, a partial write request for an address associated with the particular cache line, wherein the partial write request includes new values for a proper subset of entries in the particular cache line;
• storing, by the cache controller circuit, valid values of the partial write request in corresponding entries of the particular cache line without modifying remaining entries in the particular cache line;
• in response to the cache tag indicating the partial state, accessing, by the cache controller circuit, a mask value that identifies entries of the invalid first portion;
• receiving, by the cache controller circuit, a notification that values for one or more memory locations in a memory corresponding to one or more of the entries of the particular cache line have been modified outside of the cache memory circuit;
• and
• updating the mask value based on the notification.

A system, comprising:

• a memory circuit;
• a processor circuit configured to generate read and write requests for addresses in the memory circuit;
• and
• a cache memory system configured to:
• indicate, for a particular cache line, a partial state indicating that the particular cache line currently includes a first portion of entries that is invalid and a second portion of entries that is modified relative to memory locations at a corresponding address in the memory circuit, wherein a mask value is used to indicate the first portion of entries;
• and
• in response to receiving a notification that values for one or more memory locations in the memory circuit corresponding to one or more of the entries of the particular cache line have been modified outside of the cache memory system, update the mask value based on the notification.