US 12,007,897 B2 · Split cache for address mapping data

Abstract

Methods, systems, and devices for a split cache for address mapping data are described. A memory system may include a cache (e.g., including a first and second portion) for storing data that indicates a mapping between logical addresses associated with a host system and physical addresses of the memory system. The memory system may store data (e.g., the address mapping data) within the first portion of the cache. Additionally, the memory system may store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. The memory system may transfer subsets of the data to the second portion of the cache if they are used for access operations during the duration.

Claims20

Dependent claims

A memory system, comprising:

one or more memory devices;
and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
store data in a first portion of one or more caches of the one or more memory devices;
and
transfer the data from the first portion of the one or more caches to a second portion of the one or more caches of the one or more memory devices based at least in part on identifying that the data is used for one or more access operations while the data is stored in the first portion of the one or more caches, wherein the first portion of the one or more caches and the second portion of the one or more caches each comprise a same type of memory cells.

3 more elements

A memory system, comprising:

one or more memory devices;
one or more caches configured to store data, the one or more caches comprising a first portion configured to store data according to a first granularity and a second portion configured to store data according to a second granularity less than the first granularity, wherein the first portion of the one or more caches and the second portion of the one or more caches each comprise a same type of memory cells;
and
circuitry coupled with the one or more memory devices and the one or more caches and configured to:
transfer data from the one or more memory devices to the first portion of the one or more caches;
and
transfer a subset of the data from the first portion of the one or more caches to the second portion of the one or more caches based at least in part on the subset of the data being used for one or more access operations of the one or more memory devices while the data is stored in the first portion of the one or more caches.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/886,112Filed 11 Aug 2022 · continuation

Priority

19 Nov 2020

Published

US 2023/0015332 A119 Jan 2023

Granted

11 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 12/0848
Cache with multiple tag or data arrays being simultaneously accessible: partitioned cache, e.g. separate instruction and operand caches
G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/0804
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with main…
G06F 12/0891
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…

Family

Application16/953,075Parent of this continuation · filed 19 Nov 2020

US 2023/0015332 A1Pre-grant publication · published 19 Jan 2023

US 11,429,528 B2Parent of this continuation

US 2022/0156196 A1Published application

US 12,007,897 B2This patent

From the US filing history. Foreign family members aren’t listed.

Split cache for address mapping data

Life of this patent

Split cache for address mapping data

Life of this patent

Abstract

Claims20