Scalable system on a chip

A system on a chip (SOC), the SOC comprising:

• a plurality of processor cores;
• a plurality of graphics processing units;
• a plurality of peripheral devices;
• one or more memory controller circuits;
• and
• an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
• wherein the interconnect fabric comprises at least a first network and a second network, wherein the first network comprises one or more characteristics to reduce latency compared to the second network of the at least two networks, and wherein a given one of the one or more memory controller circuits is coupled to the first and second networks and configured to receive memory requests from both of the first and second networks;
• and
• wherein the processor cores, the graphics processing units, the peripheral devices, the one or more memory controller circuits, and the interconnect fabric are integrated onto one or more co-packaged semiconductor dies.

A system on a chip (SOC), the SOC comprising:

• a plurality of processor cores;
• a plurality of graphics processing units;
• a plurality of peripheral devices;
• one or more memory controller circuits;
• and
• an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
• wherein the interconnect fabric comprises at least a first network and a second network, wherein the first network is physically and logically independent from the second network, and wherein the first and second networks have heterogeneous interconnect topologies;
• and
• wherein the processor cores, the graphics processing units, the peripheral devices, the one or more memory controller circuits, and the interconnect fabric are integrated onto one or more co-packaged semiconductor dies.