Configurable in memory computing engine, platform, bit cells and layouts therefore

An in-memory computing architecture, comprising:

• a compute-in-memory (CIM) array of bit-cells configured to receive parallel bit-wise input signals via a first CIM array dimension and to receive one or more accumulation signals via a second CIM array dimension, wherein each plurality of bit-cells associated with a common analog accumulation signal forms a respective CIM channel configured to provide analog representation of a respective portion of a multi bit computation output signal;
• and
• control circuitry configured to cause the CIM array to perform a multi-bit computing operation on the input and accumulation signals using single-bit internal circuits and signals;
• wherein the multi-bit computing operation of the CIM array comprises bit-parallel/bit-serial (BPBS) computing, and
• wherein said bit-parallel computing comprises:
• loading different matrix-element bits into respective in-memory computing channels;
• using respective barrel shifters, barrel shifting digitized outputs from the computing channels to implement thereby corresponding bit weightings;
• and
• using respective accumulators, performing digital accumulation over all of the computing channels to yield a multi-bit matrix-element compute result;
• and
• wherein said bit-serial computing comprises:
• individually applying each bit of a vector element to the loaded matrix-element bits and storing each resulting digitized output;
• and
• using respective barrel shifters, barrel shifting the stored digitized outputs associated with each vector element bit prior to a digital accumulation with stored digitized outputs corresponding to subsequent input vector bits.