Power management of a processor and a platform in active state and low power state

An apparatus, comprising:

• a plurality of wake circuitries including first and second wake circuitry configured to implement first and second categories of wake mechanisms, respectively;
• a plurality of circuits including first and second circuits coupled to a processor, wherein the first and second wake circuitry are configured to wake up the first and second circuits, respectively;
• and
• a control circuitry coupled to the plurality of wake circuitries, wherein the control circuitry is capable of sending control messages to the plurality of wake circuitries to turn off the first and second wake circuitry when the processor is in an active operational mode.

A system, comprising:

• a processor;
• a sensor;
• a first wake circuitry;
• a second wake circuitry;
• and
• a control circuitry coupled to the processor, the sensor and the first and second wake circuitries, wherein the control circuitry is to:
• turn off the first and second wake circuitries when the processor is in an active operational mode;
• and
• when the processor is in a low power operational mode, turn on the first wake circuitry if the sensor detects a user presence, turn off the first wake circuitry if the sensor does not detect the user presence, and turn on the second wake circuitry regardless of whether the sensor detects the user presence, wherein the sensor is to continuously poll for the user presence to cause the control circuitry to selectively turn on the first wake circuitry while the second wake circuitry is turned on.