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US 12,007,441 B2Granted
3D stacked die test architecture
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
Claims20
A device comprising:
- a parallel test data input (PTDI) bus;
- a parallel test data input/output (PTDIO) bus;
- a first surface coupled to the PTDI bus and the PTDIO bus;
- a second surface opposite the first surface, wherein the second surface is coupled to the PTDI bus and the PTDIO bus;
- a first parallel test circuit coupled to the PTDI bus, wherein the first parallel test circuit includes a first parallel test data output (PTDO);
- a second parallel test circuit coupled to the PTDI bus, wherein the second parallel test circuit includes a second PTDO;
- a first comparator coupled to the first PTDO and the PTDIO bus, wherein the first comparator includes a first comparator output;
- a second comparator coupled to the second PTDO and the PTDIO bus, wherein the second comparator includes a second comparator output;
- a first gate circuit coupled to the first comparator output, wherein the first gate circuit includes an output coupled to the PTDIO bus;
- and
- a second gate circuit coupled to the second comparator output, wherein the second gate circuit includes an output coupled to the PTDIO bus.
8 more elements
A device comprising:
- a parallel test data input (PTDI) bus having a first PTDI line and a second PTDI line;
- a parallel test data input/output (PTDIO) bus having a first PTDIO line, a second PTDIO line, and a third PTDIO line;
- a first surface coupled to the PTDI bus and the PTDIO bus;
- a second surface opposite the first surface, wherein the second surface is coupled to the PTDI bus and the PTDIO bus;
- a parallel test circuit coupled to the first PTDI line and the second PTDI line, wherein the parallel test circuit includes a first parallel test data output (PTDO) and a second PTDO;
- a first comparator coupled to the first PTDO and the first PTDIO line, wherein the first comparator includes a first comparator output;
- a second comparator coupled to the second PTDO and the second PTDIO line, wherein the second comparator includes a second comparator output;
- and
- a gate circuit coupled to the first comparator output and the second comparator output,
- wherein the gate circuit includes an output coupled to the third PTDIO line.
7 more elements
Dependencies are inferred from the claim text.