Test circuit and method

An integrated circuit (IC) comprising:

• a plurality of pads at a top surface of a semiconductor wafer;
• a device-under-test (DUT) configured to receive a first alternating current (AC) signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal;
• and
• first and second detection circuits, wherein each of the first and second detection circuits comprises:
• a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device;
• a second gain stage in a cascade arrangement with the first gain stage;
• and
• a low-pass filter configured to output a direct current (DC) signal to a corresponding pad of the plurality of pads, the DC signal being based on an output signal of the second gain stage.

A method of generating test signals, the method comprising:

• using a device-under-test (DUT) to receive a first alternating current (AC) signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal;
• and
• using each of first and second detection circuits to:
• use a first gain stage coupled to a corresponding one of the first or second nodes to detect the corresponding first or second AC signal through a first capacitive device;
• use a second gain stage in a cascade arrangement with the first gain stage to generate an output signal based on a gain signal received from the first gain stage;
• and
• use a low-pass filter to generate a direct current (DC) signal based on the output signal of the second gain stage.