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US 12,007,429 B2Granted
Apparatus and method for managing power of test circuits
AssigneeIc Analytica, LLC
InventorsPatrick G. Drennan, Joseph S. Spector, Richard Wunderlich
Life of this patent
Estimating the term…
Abstract
An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.
Claims2
An apparatus, comprising:
- a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines;
- voltage regulators positioned within the scribe lines, each voltage regulator being connected to one or more test circuits, the voltage regulators being controlled by a single voltage reference signal that regulates the intended supply voltage;
- and
- selection circuitry positioned within the scribe lines, the selection circuitry governing access to a chip being tested, the selection circuitry utilizing solely pMOS transistors to direct current from the chip being tested to a selected source measurement unit.
1 more element
Dependencies are inferred from the claim text.