US 12,004,354 B2Granted

Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor

AssigneeMicron Technology, Inc.

InventorDurai Vishak Nirmal Ramaswamy

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Abstract

A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.

Claims7

Dependent claims

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:

a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;
a sense line electrically coupled to individual ones of multiple of the second source/drain regions;
the individual transistors comprising a gate insulator that is laterally between the gate and the channel region, the gate insulator being laterally between and separating the gate and the first source/drain region from physically contacting one another, the gate insulator being laterally between and separating the gate and the second source/drain region from physically contacting one another;
and
the first and second source/drain regions each have a vertical side that is directly against both of the channel region and the gate insulator, a greater quantity of each of the vertical sides of the first and second source/drain regions being directly against the gate insulator than is directly against the channel region.

5 more elements

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:

a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;
a sense line electrically coupled to individual ones of multiple of the second source/drain regions along a y-direction;
a conductive strap that is longitudinally-elongated along the y-direction, the conductive strap directly electrically coupling the pair of access-line pillars together;
and
two conductive lines that are longitudinally-elongated along an x-direction that is orthogonal to the y-direction, one of the two conductive lines directly electrically coupling together a first series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another along the x-direction, the other of the two conductive lines directly electrically coupling together a second series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another and to the first series of the conductive straps along the x-direction.

5 more elements

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:

a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;
a sense line electrically coupled to individual ones of multiple of the second source/drain regions;
a conductive strap above the pair of access-line pillars that is longitudinally-elongated and directly electrically couples the pair of access-line pillars together;
a conductive line above the conductive strap that is longitudinally-elongated along an x-direction and that directly electrically couples to the conductive strap of multiple of the pairs of access-line pillars;
and
a conductive line below the conductive line that is above the conductive strap and that is longitudinally-elongated along a y-direction that is orthogonal to the x-direction, the conductive line that is longitudinally-elongated in the y-direction directly electrically coupling together individual ones of the second capacitor electrodes.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/235,343Filed 20 Apr 2021 · division
Priority: 29 Jun 2017
Published: US 2021/0242226 A15 Aug 2021
Granted: 4 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification29 codes

H10B 53/20
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the three-dimensional [3D] arrangements, e.g. with…
H10B 12/03
For one transistor one-capacitor [1T-1C] memory cells: making the capacitor or connections thereto
H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor
H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Family

Application62/526,843Us provisional application · filed 29 Jun 2017
Application16/016,809Parent of this division · filed 25 Jun 2018
US 2021/0242226 A1Pre-grant publication · published 5 Aug 2021
US 11,011,529 B2Parent of this division
US 2019/0006376 A1Published application
US 12,004,354 B2This patent

From the US filing history. Foreign family members aren’t listed.

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