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US 12,004,350 B2Granted
Three-dimensional semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsEuntaek Jung, Joongshik Shin, Sangjun Hong
Life of this patent
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Abstract
A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.
Claims20
A three-dimensional (3D) semiconductor memory device, comprising:
- a source structure on a substrate and extending in parallel to a top surface of the substrate;
- and
- an electrode structure comprising an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source structure in a first direction that is perpendicular to the top surface of the substrate,
- wherein the erase control gate electrode is a lowest one of the gate structure and has a first thickness in the first direction, the ground selection gate electrode is a second lowest one of the gate structure and has a second thickness in the first direction, a lowermost one of the cell gate electrodes is a third lowest one of the gate structure, and each of the cell gate electrodes has a third thickness in the first direction,
- wherein the first thickness is greater than both the second thickness and the third thickness,
- wherein the ground selection gate electrode is spaced apart from the erase control gate electrode by a first maximum distance and is spaced apart from the lowermost one of the cell gate electrodes by a second maximum distance in the first direction, and
- wherein the second maximum distance is greater than the first maximum distance.
4 more elements
A three-dimensional (3D) semiconductor memory device, comprising:
- a source structure on a substrate and extending in parallel to a top surface of the substrate;
- and
- an electrode structure comprising an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source structure in a first direction that is perpendicular to the top surface of the substrate,
- wherein the erase control gate electrode is a lowest one of the electrode structure and has a first thickness in the first direction, the ground selection gate electrode is a second lowest one of the electrode structure and has a second thickness in the first direction, a lowermost one of the cell gate electrodes is a third lowest one of the electrode structure, and each of the cell gate electrodes has a third thickness in the first direction,
- wherein the ground selection gate electrode is spaced apart from the erase control gate electrode by a first maximum distance in the first direction,
- wherein the ground selection gate electrode is spaced apart from a first cell gate electrode of the cell gate electrodes by a second maximum distance in the first direction, the first cell gate electrode being the lowermost one of the cell gate electrodes in the first direction, and
- wherein the second maximum distance is greater than the first maximum distance.
4 more elements
A three-dimensional (3D) semiconductor memory device, comprising:
- a source structure on a substrate and extending in parallel to a top surface of the substrate;
- an electrode structure comprising an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source structure in a first direction that is perpendicular to the top surface of the substrate;
- a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure;
- and
- a data storage pattern extending between the vertical semiconductor pattern and the electrode structure in the first direction,
- wherein the source structure comprises:
- a first source conductive pattern on the substrate;
- and
- a second source conductive pattern in contact with a top surface of the first source conductive pattern,
- wherein the first source conductive pattern comprises:
- a horizontal portion extending in parallel to the electrode structure under the electrode structure;
- and
- a sidewall portion extending from the horizontal portion in the first direction and surrounding the portion of the sidewall of the vertical semiconductor pattern,
- wherein the erase control gate electrode is a lowest one of the electrode structure and has a first thickness in the first direction, the ground selection gate electrode is a second lowest one of the electrode structure and has a second thickness in the first direction, a lowermost one of the cell gate electrodes is a third lowest one of the electrode structure, and each of the cell gate electrodes has a third thickness in the first direction,
- wherein the first thickness is greater than the second thickness and the third thickness,
- wherein the ground selection gate electrode is spaced apart from the erase control gate electrode by a first maximum distance in the first direction,
- wherein the ground selection gate electrode is spaced apart from a first cell gate electrode of the cell gate electrodes by a second maximum distance in the first direction,
- wherein the second maximum distance is greater than the first maximum distance, and
- wherein the first cell gate electrode is closest to the ground selection gate electrode.
16 more elements
Dependencies are inferred from the claim text.