Three-dimensional memory device including self-aligned drain-select-level isolation structures and method of making thereof

A three-dimensional memory device, comprising:

• an alternating stack of insulating layers and electrically conductive layers;
• a plurality of arrays of memory openings vertically extending through the alternating stack;
• a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction;
• a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance;
• and
• drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures,
• wherein:
• the lateral offset distance comprises a uniform lateral offset distance;
• each of the drain-select-level isolation structures comprises a respective pair of lengthwise sidewalls that are vertically coincident with a subset of sidewall segments of a respective neighboring pair of dielectric plates of the plurality of dielectric plates;
• and
• the subset of sidewall segments of the respective neighboring pair of dielectric plates of the plurality of dielectric plates comprises:
• a first lengthwise sidewall that comprises a contiguous set of multiple vertically straight and laterally convex sidewall segments of one of the respective neighboring pair of dielectric plates;
• and
• a second lengthwise sidewall that comprises a contiguous set of multiple vertically straight and laterally convex sidewall segments of another of the respective neighboring pair of dielectric plates.

A three-dimensional memory device, comprising:

• an alternating stack of insulating layers and electrically conductive layers;
• a plurality of arrays of memory openings vertically extending through the alternating stack;
• a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction;
• a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance;
• and
• drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures,
• wherein each of the drain-select-level isolation structures comprises a respective pair of laterally undulating lengthwise sidewalls including a respective contiguous set of vertically straight and laterally concave sidewall segments that are adjoined to each other.

A three-dimensional memory device, comprising:

• an alternating stack of insulating layers and electrically conductive layers;
• a plurality of arrays of memory openings vertically extending through the alternating stack;
• a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction;
• a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance;
• and
• drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures,
• wherein:
• each of the memory opening fill structures comprises a respective dielectric cap structure overlying the respective vertical stack of memory elements;
• each of the plurality of dielectric plates contacts and laterally surrounds each dielectric cap structure located within a respective array of memory opening fill structures of the plurality of arrays of memory opening fill structures;
• and
• a total number of openings through each of the plurality of dielectric plates is the same as a total number of memory opening fill structures within the respective array of memory opening fill structures.

A three-dimensional memory device, comprising:

• an alternating stack of insulating layers and electrically conductive layers;
• a plurality of arrays of memory openings vertically extending through the alternating stack;
• a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction;
• a plurality of dielectric plates laterally surrounding a respective arra of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance;
• drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures;
• support pillar structures vertically extending through a subset of layers within the alternating stack;
• and
• discrete annular dielectric spacers laterally surrounding a top end of a respective one of the support pillar structures, comprising a same dielectric material as the plurality of dielectric plates, and having a uniform lateral distance between an outer sidewall and an inner sidewall that is the same as the uniform lateral offset distance.

A three-dimensional memory device, comprising:

• an alternating stack of insulating layers and electrically conductive layers;
• a plurality of arrays of memory openings vertically extending through the alternating stack;
• a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction;
• a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures bar a lateral offset distance;
• drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures;
• additional alternating stacks of additional insulating layers and additional electrically conductive layers that are laterally spaced apart from the alternating stack by a pair of line trenches that laterally extend along the first horizontal direction;
• and
• a pair of line trench fill structures comprising a respective dielectric material portion contacting a sidewall of the alternating stack and a sidewall of one of the additional alternating stacks,
• wherein additional memory opening fill structures vertically extend through the additional alternating stacks.