Semiconductor memory device and method for forming the same

A semiconductor memory device, comprising:

• a substrate;
• a plurality of bit lines, disposed on the substrate, wherein the bit lines comprise a plurality of first bit lines and at least one second bit line, the at least one second bit line being disposed outside all of the first bit lines;
• a plurality of contacts, disposed on the substrate, and alternatively and separately disposed with the bit lines;
• a dielectric layer, disposed over the contacts and the bit lines;
• a plurality of storage node pads, disposed in the dielectric layer and respectively connected to the contacts;
• and
• a capacitor structure, disposed on the storage node pads, the capacitor structure comprises a plurality of first capacitors and at least one second capacitor, the plurality of first capacitors being respectively aligned with the storage node pads, and the at least one second capacitor being located over the at least one second bit line, wherein the at least one second capacitor is isolated from any one of the contacts.

A semiconductor memory device, comprising:

• a substrate;
• a plurality of bit lines, disposed on the substrate, wherein the bit lines comprise a plurality of first bit lines and at least one second bit line, the at least one second bit line being disposed outside all of the first bit lines;
• a plurality of contacts, disposed on the substrate, and alternatively and separately disposed with the bit lines;
• a dielectric layer, disposed over the contacts and the bit lines;
• a plurality of storage node pads, disposed in the dielectric layer and respectively connected to the contacts;
• and
• a capacitor structure, disposed on the storage node pads, the capacitor structure comprises a plurality of first capacitors and at least one second capacitor, the plurality of first capacitors being respectively aligned with the storage node pads, and the at least one second capacitor being located over the at least one second bit line,
• wherein each of the bit lines comprises a semiconductor layer, a barrier layer, a conductive layer and a cap layer sequentially stacked from bottom to top, and the at least one second capacitor is in direct contact with the cap layer of the at least one second bit line.