Memory device having a diagonally opposite gate pair per memory cell

An integrated assembly, comprising:

• a memory cell that includes:
• a pillar that includes an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, a lower channel between the middle source/drain and the lower source/drain, a left-facing vertical surface facing a first direction, and a right-facing vertical surface facing a second direction that is opposite the first direction;
• an upper gate proximate to the upper channel, wherein the right-facing vertical surface faces the upper gate;
• a lower gate proximate to the lower channel, wherein the left-facing vertical surface faces the lower gate;
• and
• a capacitor that is electrically coupled with the upper source/drain;
• a digit line that, in combination with the upper gate and the lower gate, is capable of uniquely addressing the memory cell,
• wherein the digit line is beneath the pillar and is electrically coupled with the lower source/drain;
• an upper physical access line coupled to the upper gate;
• and
• a lower physical access line coupled to the lower gate,
• wherein the upper physical access line and the lower physical access line are electrically coupled to form a single logical access line that, in combination with the digit line, is capable of uniquely addressing the memory cell.

A memory device, comprising:

• a plurality of memory cells that each include:
• a pillar comprising an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain;
• and
• a gate pair that includes a first gate and a second gate,
• wherein the first gate is coupled to a first physical access line and is positioned on a first side of the pillar at a first height,
• wherein the second gate is coupled to a second physical access line and is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height, and
• wherein the first physical access line and the second physical access line are electrically coupled to form a single logical access line;
• and
• a capacitor that is electrically coupled with the upper source/drain.

A method, comprising:

• forming an electrical line;
• forming a semiconductor material on the electrical line;
• forming an electrical contact region on the semiconductor material;
• doping the semiconductor material to form a first doped region, a second doped region, and a third doped region,
• wherein the first doped region is proximate to the electrical contact region, the third doped region is proximate to the electrical line, and the second doped region is positioned between but separated from the first doped region and the third doped region;
• forming a first pillar that includes an upper source/drain that is a portion of the first doped region, a middle source/drain that is a portion of the second doped region, a lower source/drain that is a portion of the third doped region, an upper channel between the upper source/drain and the middle source/drain, a lower channel between the middle source/drain and the lower source/drain, a left-facing vertical surface facing a first direction, and a right-facing vertical surface facing a second direction that is opposite the first direction;
• forming insulative material in a first region next to the first pillar and in a second region next to the first pillar;
• forming a lower gate, in the first region, that is separated from the lower channel by the insulative material;
• forming an upper gate, in the second region, that is separated from the upper channel by the insulative material;
• and
• electrically coupling the upper gate and the lower gate by forming an upper physical access line coupled to the upper gate and a lower physical access line coupled to the lower gate,
• wherein the upper physical access line and the lower physical access line are electrically coupled to form a single logical access line.