Techniques, devices, and instruction set architecture for balanced and secure ladder computations

A processor comprising:

• a memory device;
• a plurality of registers;
• and
• one or more circuits, communicatively coupled to the memory device, to:
• store a seed number in a first memory location (ML) of the memory device, the first ML identified by a pointer stored in a first register of the plurality of registers;
• store a first number in a second ML, the second ML identified by a pointer stored in a second register of the plurality of registers;
• and
• perform a plurality of iterations, wherein for each of the plurality of iterations the one or more circuits are to:
• identify a respective bit of a plurality of bits of a second number;
• execute a conditional operation, wherein the conditional operation comprises:
• responsive to identifying that the respective bit of the plurality of bits of the second number has a defined relationship to a reference bit, swapping the pointer stored in the first register and the pointer stored in the second register;
• perform a first computational operation on at least one of a first operand identify the pointer stored in the first register or a second operand identified by the pointer stored in the second register;
• and
• determine an output of a ladder computation based on the performed plurality of iterations.

An accelerator circuit comprising:

• a first register to store a first pointer to a first memory location (ML), wherein the first ML stores a seed number;
• a second register to store a second pointer to a second ML, wherein the second ML stores a first number;
• a third register to store a first dummy pointer;
• a fourth register to store a second dummy pointer;
• a decode unit to:
• receive an instruction to perform, via a plurality of iterations, a ladder computation using the first number and a second number, wherein during each iteration of the plurality of iterations the instruction is to cause the decode unit to:
• identify a respective bit of a plurality of bits of the second number;
• perform a swapping operation comprising one of:
• responsive to the respective bit having a defined relationship to a reference bit, swapping a pointer stored in the first register with a pointer stored in the second register;
• or
• responsive to the respective bit not having the defined relationship to the reference bit, swapping a pointer stored in the third register with a pointer stored in the fourth register;
• identifying a first operand using a pointer currently stored in the first register;
• and
• identifying a second operand using a pointer currently stored in the second register;
• and
• an execution unit, wherein during each iteration of the plurality of iterations, the execution unit is to:
• perform a first computational operation on at least the first operand or the second operand;
• and
• generate an output of the ladder computation using the performed plurality of iterations.