Retimer with mesochronous intra-lane path controllers

A retimer integrated circuit (IC) comprising:

• a first signaling interface to concurrently receive a plurality of symbol streams;
• clock recovery circuitry to recover respective clock signals from the plurality of symbol streams;
• clock selection circuitry to select a first clock signal from the respective clock signals;
• a second signaling interface to concurrently output, from the retimer IC at times indicated by the first clock signal, two or more symbol streams of the plurality of symbol streams;
• and
• a programmable register, and wherein the clock selection circuitry to select the first clock signal from the respective clock signals comprises circuitry to select the first clock signal in accordance with an aggregation value and a clock-selection value stored within respective fields of the programmable register, the aggregation value indicating a subset, fewer than all, of the respective clock signals recovered from a corresponding subset of the plurality of symbol streams, and the clock-selection value specifying selection, as the first clock signal, of one clock signal from among the subset of the respective clock signals.

A method of operation within an integrated-circuit retimer (retimer IC), the method comprising:

• receiving a plurality of symbol streams concurrently via a first signaling interface;
• recovering respective clock signals from the plurality of symbol streams;
• selecting a first clock signal from the respective clock signals;
• and
• outputting from the retimer IC, concurrently via a second signaling interface, two or more symbol streams of the plurality of symbol streams at times indicated by the first clock signal;
• wherein receiving the plurality of symbol streams concurrently comprises receiving the symbol streams via respective signaling lanes coupled to the first signaling interface;
• wherein selecting the first clock signal from the respective clock signals comprises selecting the first clock signal based at least in part on lane-aggregation information that indicates aggregation of one of more subsets of the plurality of lanes into one or more multi-lane communication channels, respectively.

A method of operation within an integrated-circuit retimer (retimer IC), the method comprising:

• receiving a plurality of symbol streams concurrently via a first signaling interface;
• recovering respective clock signals from the plurality of symbol streams;
• selecting a first clock signal from the respective clock signals;
• and
• outputting from the retimer IC, concurrently via a second signaling interface, two or more symbol streams of the plurality of symbol streams at times indicated by the first clock signal;
• wherein selecting the first clock signal from the respective clock signals comprises selecting the first clock signal in accordance with an aggregation value and a clock-selection value stored within respective fields of a programmable register of the retimer IC, the aggregation value indicating a subset, fewer than all, of the respective clock signals recovered from a corresponding subset of the plurality of symbol streams, and the clock-selection value specifying selection, as the first clock signal, of one clock signal from among the subset of the respective clock signals.