Clock data recovery with decision feedback equalization
AssigneeKandou Labs, S.A.
InventorsRichard Simpson, Ali Hormati
Life of this patent
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Abstract
Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
Claims20
A method comprising:
- receiving a data signal over a series of signaling intervals that forms a signaling eye for a data pattern of a plurality of data patterns, the plurality of data patterns comprising transitioning data patterns;
- filtering the data signal to align transitioning signal edge trajectories of each transitioning data pattern with a corresponding one of a plurality of speculative decision feedback equalization (DFE) decision thresholds;
- generating, for each speculative DFE decision threshold, a corresponding sample of the data signal using a respective sampler according to a sampling clock, wherein the corresponding sample for a given DFE decision threshold corresponds to (i) a data decision for a first subset of the plurality of data patterns, (ii) an edge sample for a second subset of the plurality of data patterns, and (iii) neither a data decision nor an edge sample for a third subset of the plurality of data patterns;
- generating phase-error signals based on each edge sample;
- and
- providing the phase-error signals to a clock recovery circuit to adjust the sampling instant of the sampling clock.
An apparatus comprising:
- a continuous time linear equalizer (CTLE) configured to receive a data signal comprising a plurality of data patterns over a series of signaling intervals and to filter the data signal to generate a filtered data signal having altered signal trajectories;
- a voltage comparator configured to generate a sample of the filtered data signal responsive to a sampling clock and according to a decision threshold associated with a decision feedback equalizer coefficient;
- a data pattern detection circuit configured to identify a specific data pattern associated with the sample;
- and
- a selection circuit configured to responsively process the sample as (i) a valid data decision, (ii) a phase error sample to provide to a clock recovery circuit for adjusting the sampling clock, or (iii) an unneeded sample which may be ignored.
A method comprising:
- receiving a data signal comprising a plurality of data patterns over a series of signaling intervals and filtering the data signal to generate a filtered data signal having altered signal trajectories;
- generating a sample of the filtered data signal responsive to a sampling clock and according to a decision threshold associated with a decision feedback equalizer coefficient;
- identifying a specific data pattern associated with the sample;
- and
- processing the sample as (i) a valid data decision, (ii) a phase error sample to provide to a clock recovery circuit for adjusting the sampling clock, or (iii) an unneeded sample which may be ignored.
Dependencies are inferred from the claim text.