10G rate OLT terminal transceiver integrated chip based on EPON with EML laser

A 10G rate OLT terminal transceiver integrated chip based on EPON with EML laser, comprising:

• a burst mode receiver RX, a continuous mode transmitter TX and a digital control unit DIGITAL, and a power module POWER;
• wherein the burst mode receiver RX amplifies an electrical signal which is originated from an optical signal from each ONU client and processed through a burst mode receiver TIA, and the burst mode receiver RX comprises two channels with different rates and selects one of the two channels to open, defining a working channel, so the electrical signal is output from the working channel;
• the continuous mode transmitter TX receives the electrical signal attenuated by a PCB board, and in response to a degree of attenuation, selects a bypass path BYPASS for transmission or outputs the electrical signal after a signal quality of the electrical signal is processed and improved by a clock data recovery path CDR to drive the EML laser;
• the digital control unit DIGITAL controls a path selection of the continuous mode transmitter TX according to an external command;
• a host controls the channel selection of the burst mode receiver RX through a chip pin RS;
• and
• the power module POWER is arranged to provide power supply to the chip;
• wherein the power module POWER comprises a DC power supply VDC, a DC chopper DC/DC, and resistors R1 and R2;
• wherein the DC power supply VDC provides working power for the EML laser driver while the DC chopper DC/DC converts the DC power supply VDC into a DC power supply VCC1 and outputs it through a pin VOUT;
• the DC power supply VCC1 provides working power for the burst mode receiver RX, the continuous mode transmitter TX and the digital control unit Digital respectively;
• an output terminal VOUT of the DC chopper DC/DC is connected to one end of the resistor R1 and a chip pin CAP1 simultaneously;
• the chip pin CAP1 is grounded through a capacitor C2;
• another end of the resistor R1 is simultaneously connect to one end of the resistor R2 and a feedback signal terminal FB of the DC chopper DC/DC;
• another end of the resistor R2 is grounded;
• a switch input port SW of the DC chopper DC/DC is connected to a chip pin SW1, the chip pin SW1 is connected to a positive terminal of the DC power supply VDC through and inducer L1,
• a power supply voltage port VCC of the DC chopper DC/DC is connected to a chip pin VDC;
• the chip pin VDC is connected to the positive terminal of the DC power supply VDC;
• and
• an enable port EN of the DC chopper DC/DC is connected to a chip pin EN1;
• the chip pin EN1 is connected to one end of a capacitor C1 and the positive terminal of the DC power supply VDC at the same time;
• another end of the capacitor C1 is grounded, and a negative terminal of the DC power supply VDC is grounded.