Integrated circuit having latch with transistors of different gate widths

An integrated circuit comprising:

• a wide type-one active-region structure and a wide type-two active-region structure extending in a first direction;
• a narrow type-one active-region structure and a narrow type-two active-region structure extending in the first direction;
• wide type-one transistors in the wide type-one active-region structure and narrow type-one transistors in the narrow type-one active-region structure, wherein an average gate width of the wide type-one transistors is larger than an average gate width of the narrow type-one transistors;
• wide type-two transistors in the wide type-two active-region structure and narrow type-two transistors in the narrow type-two active-region structure, wherein an average gate width of the wide type-two transistors is larger than an average gate width of the narrow type-two transistors;
• a clock gated input circuit, a first inverter, and an output driver constructed with the wide type-one transistors and the wide type-two transistors, wherein the first inverter is coupled between an output of the clock gated input circuit and an input of the output driver;
• and
• a first clocked inverter constructed with the narrow type-one transistors and the narrow type-two transistors, wherein the first clocked inverter is coupled between an output of the first inverter and an input of the first inverter and forms a latch.

A method comprising:

• fabricating a wide type-one active-region structure and a narrow type-one active-region structure extending in a first direction, wherein an average width of the wide type-one active-region structure is larger than an average width of the narrow type-one active-region structure;
• fabricating a wide type-two active-region structure and a narrow type-two active-region structure extending in the first direction, wherein an average width of the wide type-two active-region structure is larger than an average width of the narrow type-two active-region structure;
• forming a first inverter, a first transmission gate, and a second inverter with wide type-one transistors in the wide type-one active-region structure and wide type-two transistors in the wide type-two active-region structure, wherein the first transmission gate is coupled between an output of the first inverter and an input of the second inverter;
• forming a first clocked inverter and a second clocked inverter with narrow type-one transistors in the narrow type-one active-region structure and narrow type-two transistors in the narrow type-two active-region structure;
• and
• connecting an input of the first clocked inverter with the output of the first inverter, connecting the output of the first clocked inverter with an input of the first inverter, connecting an input of the second clocked inverter with an output of the second inverter, and connecting an output of the second clocked inverter with the input of the second inverter.