Controlling duty cycle distortion with a mixed-signal circuit

An electronic device, comprising:

• an input circuit unit for generating a first periodic signal and a second periodic signal based on a plurality of parallel data and an input clock signal, wherein the first periodic signal is enabled in each high voltage duty cycle of the input clock signal, and the second periodic signal is enabled in each low voltage duty cycle of the input clock signal;
• and
• a module unit coupled to the input circuit unit and including a low pass filter unit, the low pass filter unit configured to generate a first output voltage and a second output voltage based on the first periodic signal and the second periodic signal, wherein:
• the first output voltage has a first direct current (DC) voltage level indicating a first cycle length of high voltage duty cycles of the input clock signal in real time;
• the second output voltage has a second DC voltage level indicating a second cycle length of low voltage duty cycles of the input clock signal in real time;
• a difference between the first and second DC voltage levels corresponds to a duty cycle distortion level of the input clock signal;
• and
• the module unit is configured to generate a duty cycle control signal to control the high voltage duty cycle of the input clock signal based on the first and second output voltages.

A method for controlling duty cycle distortion of clock signals, comprising:

• obtaining an input clock signal;
• generating a first output voltage and a second output voltage, wherein:
• the first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal;
• the second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal;
• a difference between the first DC voltage level and the second DC voltage level corresponds to a duty cycle distortion level of the input clock signal;
• based on the difference between the first DC voltage level and the second DC voltage level, generating a duty cycle control signal to control the high voltage duty cycles of the input clock signal, wherein the duty cycle control signal includes a multi-bit digital control signal;
• and
• controlling the duty cycles of the input clock signal by selecting a first delay time of a first plurality of delay times for the input clock signal by the multi-bit digital control signal.