Low-power flip flop circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chia Lai, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
Life of this patent
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Abstract
A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
Claims20
A method to operate a flip-flop circuit, comprising:
- receiving a scan-in signal and a data signal;
- selectively coupling either the scan-in signal or the data signal to coupled master and slave latches;
- and
- based on a clock signal, selectively activating either the master latch or the slave latch so as to latch either the scan-in signal or the data signal as an output signal of the flip-flop circuit, wherein the master latch circuit comprises a pair of cross-coupled AND-OR-Inverter (AOI) logic gates, and the slave latch circuit comprises a pair of cross-coupled OR-AND-Inverter (OAI) logic gates;
- providing a logically inverted clock signal to the master latch circuit and the slave latch circuit, respectively;
- and
- delaying the clock signal to the master latch circuit but not delaying the clock signal to the slave latch circuit.
A method to operate a flip-flop circuit, comprising:
- receiving a scan-in signal and a data signal;
- selectively coupling either the scan-in signal or the data signal to coupled master and slave latches;
- based on a clock signal, selectively activating either the master latch or the slave latch so as to latch either the scan-in signal or the data signal as an output signal of the flip-flop circuit, wherein the master latch circuit comprises a pair of cross-coupled AND-OR-Inverter (AOI) logic gates, and the slave latch circuit comprises a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and wherein the master and slave latch circuits each comprises at most two transistors configured to receive the clock signal;
- and
- providing a logically inverted clock signal to the at most two transistors of the master latch circuit and the at most two transistors of the slave latch circuit, respectively.
A method to operate a flip-flop circuit, comprising:
- receiving a scan-in signal at a first input of a multiplexer;
- receiving a data signal at a second input of the multiplexer;
- receiving a scan-enable signal at a third input of the multiplayer, wherein a logic state of the scan-enable signal selectively couples either the scan-in signal or the data signal to a master latch circuit and a slave latch circuit, wherein the master latch circuit comprises a pair of cross-coupled AND-OR-Inverter (AOI) logic gates, and the slave latch circuit comprises a pair of cross-coupled OR-AND-Inverter (OAI) logic gates;
- based on a clock signal, selectively activating either the master latch circuit or the slave latch circuit so as to latch either the scan-in signal or the data signal as an output signal of the flip-flop circuit;
- and
- providing a logically inverted clock signal to the master and slave latch circuits, respectively,
- wherein the master and slave latches each comprises at most two transistors configured to receive the clock signal.
Dependencies are inferred from the claim text.